CS61574-IL Cirrus Logic, Inc., CS61574-IL Datasheet - Page 13

• Manufacturer Part Number: CS61574-IL
• Description: Interface, T1/E1 Line Interface
• Manufacturer: Cirrus Logic, Inc.

X = Don’t Care
Loss of Signal
The receiver will indicate loss of signal after
power-up, reset or upon receiving 175 consecu-
tive zeros. A digital counter counts received
zeros, based on RCLK cycles. A zero is received
when the RTIP and RRING inputs are below the
input comparator slicing threshold level estab-
lished by the peak detector. After the signal is
removed for a period of time the data slicing
threshold level decays to approximately
300 mV
The receiver reports loss of signal by setting the
Loss of Signal pin, LOS, high. If the serial inter-
face is used, the LOS bit will be set and an
interrupt will be issued on INT (unless disabled).
LOS will return low (asserting the INT pin again
in Host Mode) upon receipt of 3 ones in 32 bit
periods with no more than 15 consecutive zeros.
Note that in the Host Mode, LOS is simultane-
ously available from both the register and pin 12.
RPOS/RNEG or RDATA are forced low during
LOS unless the jitter attenuator is disabled. (See
"Jitter Attenuator" section)
If ACLKI is present during the LOS state, ACLKI
is switched into the input of the jitter attenuator,
resulting in RCLK matching the frequency of
ACLKI. The jitter attenuator buffers any instanta-
neous changes in phase between the last
recovered clock and the ACLKI reference clock.
DS155PP2
(>(V+) - 0.2V)
(>(V+) - 0.2V)
MIDDLE
(<0.2V)
MODE
(pin 5)
(2.5V)
HIGH
HIGH
LOW
Table 5. Data Output/Clock Relationship
peak
.
(pin 28)
CLKE
HIGH
LOW
X
X
RDATA
RNEG
RNEG
RNEG
RPOS
RPOS
RPOS
DATA
SDO
SDO
CLOCK
RCLK
RCLK
RCLK
RCLK
SCLK
RCLK
RCLK
SCLK
RCLK
Clock Edge for
Valid Data
Rising
Rising
Rising
Rising
Falling
Falling
Falling
Rising
Falling
This means that RCLK will smoothly transition
to the new frequency. If ACLKI is not present,
then the crystal oscillator of the jitter attenuator is
forced to its center frequency. Table 6 shows the
status of RCLK upon LOS.
Jitter Attenuator
The jitter attenuator reduces wander and jitter in
the recovered clock signal. It consists of a 32-bit
FIFO, a crystal oscillator, a set of load capacitors
for the crystal, and control logic. The jitter attenu-
ator exceeds the jitter attenuation requirements of
Publications 43802 and REC. G.742.
The jitter attenuator works in the following man-
ner. The recovered clock and data are input to the
FIFO with the recovered clock controlling the
FIFO’s write pointer. The crystal oscillator con-
trols the FIFO’s read pointer which reads data out
of the FIFO and presents it at RPOS and RNEG
(or RDATA). The update rate of the read pointer
is analogous to RCLK. By changing the load ca-
pacitance that the IC presents to the crystal, the
oscillation frequency is adjusted to the average
frequency of the recovered signal. Logic deter-
mines the phase relationship between the read and
write pointers and decides how to adjust the load
capacitance of the crystal. Thus the jitter attenu-
ator behaves as a first-order phase lock loop. Jitter
is absorbed in the FIFO according to the jitter
transfer characteristic shown in Figure 12.
present?
Crystal
Yes
Yes
No
Table 6. RCLK Status at LOS
present?
ACLKI
Yes
Yes
No
Centered Crystal
Source of RCLK
Jitter Attenuator
ACLKI via the
ACLKI
CS61577
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