CS61574-IL Cirrus Logic, Inc., CS61574-IL Datasheet - Page 14

• Manufacturer Part Number: CS61574-IL
• Description: Interface, T1/E1 Line Interface
• Manufacturer: Cirrus Logic, Inc.

The FIFO in the jitter attenuator is designed to
prevent overflow and underflow. If the jitter am-
plitude becomes very large, the read and write
pointers may get very close together. Should they
attempt to cross, the oscillator’s divide by four
circuit adjusts by performing a divide by 3 1/2 or
divide by 4 1/2 to prevent the overflow or under-
flow. During this activity, data will never be lost.
The 32-bit FIFO in the CS61577 attenuator al-
lows it to absorb jitter with minimum data delay
in T1 and E1 switching or transmission applica-
tions. Like the CS61574, the CS61577 will
tolerate large amplitude jitter (>23 UIpp) by
tracking rather than attenuating it, preventing data
errors so that the jitter may be absorbed in exter-
nal frame buffers.
The jitter attenuator may be bypassed by pulling
XTALIN to RV+ through a 1 k resistor and pro-
viding a 1.544 MHz (or 2.048 MHz) clock on
ACLKI. RCLK may exhibit quantization jitter of
approximately 1/13 UIpp and a duty cycle of ap-
proximately 30% (70%) when the attenuator is
disabled.
14
10
20
30
40
50
60
0
1
Figure 12. Typical Jitter Transfer Function
b) Maximum
Attenuation
Limit
10
a) Minimum Attenuation Limit
100
Frequency in Hz
62411 Requirements
Measured Performance
1 k
10 k
Local Loopback
Local loopback is selected by taking LLOOP, pin
27, high or by setting the LLOOP register bit via
the serial interface.
The local loopback mode takes clock and data
presented on TCLK, TPOS, and TNEG (or
TDATA), sends it through the jitter attenuator and
outputs it at RCLK, RPOS and RNEG (or
RDATA). If the jitter attenuator is disabled, it is
bypassed. Inputs to the transmitter are still trans-
mitted on TTIP and TRING, unless TAOS has
been selected in which case, AMI-coded continu-
ous ones are transmitted at the TCLK frequency.
The receiver RTIP and RRING inputs are ignored
when local loopback is in effect.
Remote Loopback
Remote loopback is selected by taking RLOOP,
pin 26, high or by setting the RLOOP register bit
via the serial interface.
In remote loopback, the recovered clock and data
input on RTIP and RRING are sent through the
jitter attenuator and back out on the line via TTIP
and TRING. Selecting remote loopback overrides
any TAOS request (see Table 6). The recovered
incoming signals are also sent to RCLK, RPOS
and RNEG (or RDATA). A remote loopback oc-
curs in response to RLOOP going high.
Notes: 1. X = Don’t Care. The identified All Ones Select
RLOOP
Signal
Input
0
0
1
Table 7. Interaction of RLOOP with TAOS
2. Logic 1 indicates that Loopback or All Ones
Signal
TAOS
Input
input is ignored when the indicated loopback is
in effect.
option is selected.
X
0
1
RTIP & RRING RTIP & RRING (RCLK)
TTIP & TRING
Source of
Data for
TDATA
all 1s
TTIP & TRING
Source of
Clock for
CS61577
TCLK
TCLK
DS155PP2