STE2002DIE1 STMicroelectronics, STE2002DIE1 Datasheet
STE2002DIE1
Related parts for STE2002DIE1
STE2002DIE1 Summary of contents
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... DATA INSTRUCTION REGISTER REGISTER I 2 CBUS PARALLEL SCL SDA_IN SDA_OUT DB0 to DB7 E PD/C R/W STE2002 2 C) for ease of interfacing with the Type Ordering Number STE2002DIE1 STE2002DIE2 R0 to R80 ICON ROW DRIVERS SHIFT REGISTER SCROLL LOGIC TEST_1_14 TEST ICON_MODE DISPLAY EXT CONTROL BSY_FLG LOGIC ...
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STE2002 PIN DESCRIPTION N° Pad Type R0 to R80 129-169 O 282-322 ICON 323 C127 1-128 O V 236-255 GND SS V 188-199 Supply DD1 V 200-211 Supply DD2 V 261-270 Supply LCDIN V 273-282 Supply LCDOUT ...
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PIN DESCRIPTION (continued) N° Pad Type SCLK 217 I SCE 216 I SD/C 215 I SOUT 213 O BSYFLG 212 T14 170-179, I/O 256-259 Serial Interface Clock Serial Interface ENABLE. When Low the Incoming Data are Clocked ...
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STE2002 Figure 2. Chip Mechanical Drawing COL COL 63 COL 64 COL 127 4/51 MARK_1 0 STE2002 VLCDOUT VLCDSENSE (0, MARK_2 ROW 35 ROW 39. VLCDOUT VLCDSENSE VLCDIN VLCDIN MARK_3 OSCOUT TEST_14 TEST_13 TEST_12 TEST_11 VSS SCL SDAIN ...
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Figure 3. Improved ALTH & PLESKO Driving Method V LCD ROW LCD ROW ...
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STE2002 CIRCUIT DESCRIPTION Supplies Voltages and Grounds V is supply voltages to the internal voltage generator (see below). If the internal voltage generator is DD2 not used, this should be connected to V could be different form V . DD2 ...
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The STE2002 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below: BS2 The following table Bias Level for and are ...
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STE2002 Temperature Coefficient As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's the need to vary the LCD Voltage with temperature. The STE2002 provides the possibility to change the VLCD in a ...
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Display Data RAM The STE2002, provides an 104X128 bits Static RAM to store Display data. This is organized into 13 (Bank0 to Bank12) banks with 128 Bytes. One of these banks (128 bits wide) can be used for Icons. RAM ...
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STE2002 Figure 6. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0) 0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK ...
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Figure 10. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX= BANK 0 BANK 1 BANK 2 Y CARR BANK 11 BANK 12 Figure 11. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=0) ...
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STE2002 Figure 14. Data RAM Byte organization with MSB BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 LSB BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 Figure ...
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Figure 18. Memory Rows vs. Row drivers mapping with MY=0, MUX 81, SCROLL POINTER=+3, ICON MODE=0 ROW DRIVER PHYSICAL MEMORY ROW ICON MODE ROW ROW ROW ROW ...
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STE2002 Figure 21. Memory Rows vs. Row drivers mapping with MUX65, Y-CARRIAGE>8, SCROLL POINTER=3, ICON MODE=1, PHYSICAL MEMORY ROW ROW DRIVER 0 ROW ROW 1 ROW ROW 33 N. ROW ...
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Figure 24. Memory Rows vs. Row drivers mapping with MY=1, MUX81, SCROLL OFFSET= +3, ICON MODE =1 ROW DRIVER PHYSICAL MEMORY ROW ICON MODE ROW ROW ROW ROW 3 ...
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STE2002 Figure 26. Row Drivers vs. LCD Panel Interconnection in MUX65 Mode ROW DRIVERS Figure 27. Row Drivers vs. LCD Panel Interconnection in MUX49 Mode ROW DRIVERS 16/51 ICON 65x128 MUX 65 Mode COLUMN DRIVERS R40 R41 R42 R43 R44 ...
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Figure 28. Row Drivers vs. LCD Panel Interconnection in MUX33 Mode ROW DRIVERS Instruction Set Two different instructions formats are provided: - With D/C set to LOW commands are sent to the Control circuitry. - With D/C set to HIGH ...
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STE2002 Power Down ( When at Power Down, all LCD outputs are kept at V are OFF (V output is discharged to V LCDOUT Oscillator is in off state. An external clock can be provided. The RAM contents ...
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MUX RATE ICON MODE MUX 33 1 MUX 33 0 MUX 49 1 MUX 49 0 MUX 65 1 MUX 65 0 MUX 81 1 MUX 81 0 Dual Partial Display If the PE Bit is set to a logic ...
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STE2002 Bus Interfaces To provide the widest flexibility and ease of use the STE2002 features three different methods for interfacing the host Controller. To select the desired interface the SEL1 and SEL2 pads need to be connected to a logic ...
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Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the ac- knowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from ...
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STE2002 the second is a data byte (fig 31). The Co bit is the command MSB and defines if after this command will follow one data byte and an other command word or if will follow a stream of data ...
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If SCE stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte at the next SCLK positive edge. A reset pulse on RES pin interrupts the transmission. No data is ...
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STE2002 Figure 35. Reading Sequence note: 1) these data are not read by the display Diver Parallel Interface The STE2002 parallel Interface is a bidirectional link between the display driver and the application supervisor. It consists of eleven lines: eight ...
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Table 1. STE2001-like instruction Set Instruction D/C R/W H Function Set 0 0 Read Status Byte 0 1 Write Data 1 0 H=0 Memory Blank 0 0 Scroll Range Setting 0 0 LCD ...
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STE2002 Table 2. Extended Instruction Set Instruction D/C R/W NOP 0 0 Function Set 0 0 Read Status Byte 0 1 Write Data 1 0 Memory Blank 0 0 Scroll Range Setting 0 0 LCD Display Control ...
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Table 3. Explanations of Table 2 symbols BIT 0 DIR Scroll by one down PD Device fully working V Horizontal addressing MX Normal X axis addressing MY Image is displayed not vertically mirrored DO MSB on TOP PE Partial Display ...
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STE2002 Table 8. MULTIPLEXING RATIO M[1] M[ Table 9. TEMPERATURE COEFFICIENT ...
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Table 13. Y CARRIAGE RETURN REGISTER Y-C[3] Y-C[2] Y-C[1] Y-C[ ...
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STE2002 Figure 36. Host Processor Interconnection with I2C Interface Figure 37. Host Processor Interconnection with Serial Interface 30/51 SCL SDAIN SDAOUT STE2002 VSSAUX RES E PD R/W VSSAUX SCLK SCE SD/C SDIN ...
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Figure 38. Host Processor Interconnection with Parallel Interface Figure 39. Application Schematic Using an External LCD Voltage Generator V DD 100nF LCD SCL SDAIN SDAOUT STE2002 VSSAUX RES E PD ...
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STE2002 Figure 40. Application Schematic using the Internal LCD Voltage Generator and two separate supplies V DD2 100nF Figure 41. Application Schematic using the Internal LCD Voltage Generator and a single supply 32/51 I/O VDD2 V ...
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Figure 42. Power-Up sequence VDD2 VDD1 RES SCE SCLK SDIN SD/C PD HOST Hi-Z DRIVER SCL SDAIN SOUT Hi-Z SDA OUT OSCIN (HOST) OSC OUT (DRIVER) BSY FLG vdd ...
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STE2002 Figure 43. Power-OFF Sequence VDD2 VDD1 RES SCLK SDIN SD/C PD/C E SCE SCl SDAIN R HOST DRIVER SOUT SDA OUT OSCIN (HOST) OSC OUT (DRIVER) BSY FLG 34/51 T w(res) Hi-Z Hi-Z ...
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Figure 44. Initialization with built-in Booster Figure 45. Dual Partial Display Enabling Instruction Flow SETUP NORMAL DISPLAY MODE CONFIGURATION SET Driver in Power Down(PD=1) SET Driver in Normal Display Mode (PE=0) SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0], FR[1:0], TC, M[1:0] for ...
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STE2002 Figure 46. Dual Partial Display Mode configuration or Duty Change 36/51 SETUP PARTIAL DISPLAY CONFIGURATION SET Driver in Power Down(PD=1) SET Driver in Partial Display Mode (PE=1) SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0] for Partial Display Operation SET Partial Display ...
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Figure 47. DATA RAM to display Mapping DISPLAY DATA RAM bank 0 bank 1 bank 2 bank 3 bank 7 bank 8 Table 15. Test Pin Configuration Test Numb. TEST_1 TEST_2 TEST_3 TEST_4 TEST_5 TEST_6 TEST_7 TEST_8 TEST_9 TEST_10 TEST_11 ...
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STE2002 ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Range DD1 V Supply Voltage Range DD2 V LCD Supply Voltage Range LCD I Supply Current SS V Input Voltage (all input pads Input Current Output ...
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ELECTRICAL CHARACTERISTICS (continued) DC OPERATION (V = 1 1.75 to 4.2V; V DD1 DD2 Symbol Parameter Logic Inputs V Logic LOW voltage level IL V Logic HIGH Voltage Level IH I Input Current in Logic ...
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STE2002 ELECTRICAL CHARACTERISTICS AC OPERATION (V = 1.7 to 3.6V 1.75 to 4.2V; V DD1 DD2 Symbol Parameter INTERNAL OSCILLATOR F Internal Oscillator frequency OSC F External Oscillator frequency EXT F Frame frequency FRAME T RES LOW pulse ...
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ELECTRICAL CHARACTERISTICS AC OPERATION (V = 1.7 to 3.6V 1.75 to 4.2V; V DD1 DD2 Symbol Parameter BUS INTERFACE (See note 4) F SCL Clock Frequency SCL T Set-up time (repeated) START SU;STA condition T ...
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STE2002 ELECTRICAL CHARACTERISTICS (continued) AC OPERATION (V = 1.7 to 3.6V 1.75 to 4.2V; V DD1 DD2 Symbol Parameter PARALLEL INTERFACE T Enable Cycle Time CY(EN) T Enable Pulse width W(EN) T Address Set-up Time SU(A) T Address ...
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ELECTRICAL CHARACTERISTICS (continued) AC OPERATION (V = 1.7 to 3.6V 1.75 to 4.2V; V DD1 DD2 Symbol Parameter SERIAL INTERFACE T Clock Cycle SCLK CYC T SCLK pulse width HIGH PWH1 T SCLK Pulse width LOW PWL1 SCE ...
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STE2002 Table 16. Pad Coordinates NAME PAD -3275 -3225 -3175 -3125 -3075 -3025 -2975 -2925 -2875 -2825.0 ...
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Table 16. Pad Coordinates (continued) NAME PAD C62 63 -175.0 C63 64 -125.0 C64 65 +125.0 C65 66 +175.0 C66 67 +225.0 C67 68 +275.0 C68 69 +325.0 C69 70 +375.0 C70 71 +425.0 C71 72 +475.0 ...
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STE2002 Table 16. Pad Coordinates (continued) NAME PAD C124 125 +3125.0 C125 126 +3175.0 C126 127 +3225.0 C127 128 +3275.0 R40 129 +3571.5 R41 130 +3571.5 R42 131 +3571.5 R43 132 +3571.5 R44 133 +3571.5 R45 134 ...
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Table 16. Pad Coordinates (continued) NAME PAD OSC_IN 187 +1875.0 VDD1_1 188 +1825.0 VDD1_2 189 +1825.0 VDD1_3 190 +1775.0 VDD1_4 191 +1775.0 VDD1_5 192 +1725.0 VDD1_6 193 +1725.0 VDD1_7 194 +1675.0 VDD1_8 195 +1675.0 VDD1_9 196 +1625.0 ...
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STE2002 Table 16. Pad Coordinates (continued) NAME PAD VSS_14 249 -1275.0 VSS_15 250 -1325.0 VSS_16 251 -1325.0 VSS_17 252 -1375.0 VSS_18 253 -1375.0 VSS_19 254 -1425.0 VSS_20 255 -1425.0 TEST_11 256 -1475.0 TEST_12 257 -1525.0 TEST_13 258 ...
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Table 16. Pad Coordinates (continued) NAME PAD R11 311 -3571.5 R10 312 -3571.5 R9 313 -3571.5 R8 314 -3571.5 R7 315 -3571.5 R6 316 -3571.5 R5 317 -3571.5 R4 318 -3571.5 R3 319 -3571.5 R2 320 -3571.5 ...
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STE2002 Figure 55. DIE ORIENTATION IN TRAY Mark 1 Figure 56. TRAY INFORMATION A A 50/51 Mark 3 Mark 4 STE2002 DIE IDENTIFICATION Mark 2 Array Size = 13 x5 (65) Units ...
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