STE2004DIE1 STMicroelectronics, STE2004DIE1 Datasheet
STE2004DIE1
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STE2004DIE1 Summary of contents
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... STE2004 features six standard interfaces (3-lines Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel, 8080 parallel & I host micro-controller ) Table 1. Order Codes X Part Numbers STE2004DIE1 STE2004DIE2 CO to C101 TIMING OSC GENERATOR COLUMN DRIVERS MASTER CLOCK ...
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STE2004 Table 2. Pin Description N° Pad Type R0 to R64 1-6 O 109-141 C0 to C101 6-107 O V 192-203 GND SS V 156-163 Supply DD1 V 164-171 Supply DD2 V 205-209 Supply LCD V 204 Supply LCDSENSE V ...
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Table 2. Pin Description (continued) N° Pad Type 176 RES 172 D/C 174 CS 173 TEST_MODE 191 TEST_VREF 146 O OSCIN 144 OSCOUT 210 O FR_OUT 211 O FR_IN 143 M/S 100 8080 Series ...
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STE2004 Figure 2. Chip Mechanical Drawing COL 50 COL 51 COL 101 ROW 32 ROW 37 4/66 MARK_1 ROW 5 ROW 0 COL 0 MARK_3 STE2004 (0, MARK_4 MARK_2 ROW28 ROW31 FR_OUT OSC_OUT VLCD VLCDSENSE VSS TEST_MODE VSSAUX ...
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Figure 3. Improved ALTH & PLESKO Driving Method V LCD ROW LCD ROW ...
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STE2004 3 CIRCUIT DESCRIPTION 3.1 Supplies Voltages and Grounds V is supply voltages to the internal voltage generator (see below). If the internal voltage generator is DD2 not used, this should be connected to V could be different form V ...
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Figure 4. Master Slave Logic Connection with frame Synchronization STE2004 VDD1AUX OSCIN FRIN Figure 5. Master Slave Logic Connection without frame Synchronization STE2004 VDD1AUX OSCIN FRIN 3.5 Bias Levels To properly drive the LCD, six (Including VLCD and VSS) different ...
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STE2004 Table 3. BS2 The following table Bias Level for and are provided: Table 4. Symbol 3.6 LCD Voltage Generation ...
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Temperature Coefficients As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's the need to vary the LCD Voltage with temperature. STE2004 provides the possibility to change the VLCD in a linear ...
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STE2004 3.8 Display Data RAM The STE2004, provides an 102X65 bits Static RAM to store Display data. This is organized into 9 (Bank0 to Bank8) banks with 102 Bytes. One of these Banks can be used for Icons. RAM access ...
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Figure 8. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0) 0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 Figure 9. Automatic data RAM writing ...
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STE2004 Figure 12. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX= BANK 0 BANK 1 BANK 2 Y CARR BANK 7 BANK 8 Figure 13. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; ...
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Figure 16. Data RAM Byte organization with MSB BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 LSB BANK 5 BANK 6 BANK 7 BANK 8 Figure 17. Data RAM Byte organization with ...
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STE2004 Figure 18. Memory Rows vs. Row Drivers Mapping ICON_MODE=1 and MUX Address ...
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Figure 19. Memory Rows vs. Row Drivers Mapping ICON_MODE=0 and MUX Address ...
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STE2004 Figure 20. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=6 and MUX Address ...
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Figure 21. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage<=6 and MUX Address ...
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STE2004 Figure 22. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=7, Scrolling Pointer>07h and MUX Address ...
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Figure 23. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=7, Scrolling Pointer>07h and MUX Address ...
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STE2004 Figure 24. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=8, Scrolling Pointer<10h and MUX Address ...
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Figure 25. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=8, Scrolling Pointer<10h and MUX Address ...
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STE2004 Figure 26. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=4 and MUX33 D Y Address ...
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Figure 27. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage<=4 and MUX Address ...
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STE2004 Figure 28. Row Drivers vs. LCD Panel Interconnection in MUX65 Mode ROW DRIVERS Figure 29. Row Drivers vs. LCD Panel Interconnection in MUX49 Mode ROW DRIVERS 24/66 ICON MUX 65 COLUMN DRIVERS R32 R33 R34 R35 R36 R37 R38 ...
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Figure 30. Row Drivers vs. LCD Panel Interconnection in MUX33 Mode ROW DRIVERS ICON MUX 33 COLUMN DRIVERS R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 STE2004 R45 R46 R47 R48 R49 R50 R51 R52 ...
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STE2004 4 BUS INTERFACES To provide the widest flexibility and ease of use the STE2004 features Six different methods for interfacing the host Controller. To select the desired interface the SEL1, SEL2 and SEL3 pads need to be connected to ...
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The device that acknowledges has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an end-of-data to ...
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STE2004 4.1.2 Writing Mode. If the R/W bit is set to logic 0 the STE2004 is set receiver. After the slaves acknowledge one or more command word follows to define the status of the device. A command ...
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SCLK clock pulse during every byte transfer stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte at the next SCLK positive edge. A reset pulse ...
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STE2004 Figure 37. 4-lines SPI Reading Sequence note: 1) these data are not read by the display Diver 4.2.2 3-lines SPI Interface The STE2004 3-lines serial Interface is a bidirectional link between the display driver and the application supervisor. It ...
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Figure 38. 3-lines serial interface protocol in Writing Mode WRITE MODE 1 Control Byte DATA Byte Co COMMAND WORD Control Byte 0 0 DATA Byte LAST CONTROL BYTE Control Byte 0 1 DATA Byte LAST CONTROL BYTE Figure 39. 3-lines ...
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STE2004 Figure 40. 3-lines SPI Reading Sequence 4.2.3 3-lines 9 bits Serial Interface The STE2004 3-lines serial Interface is a bidirectional link between the display driver and the application supervisor. It consists of three lines: one/two for data signals (SDIN, ...
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Figure 41. 3-lines serial bus protocol - one byte transmission CS SCLK SDIN SD/C MSB Figure 42. 3-lines serial bus protocol - several byte transmission CS SCLK SDIN D/C DB7 DB6 DB5 Figure 43. 3-lines serial interface protocol in Reading ...
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STE2004 4.3 Parallel Interface The STE2004 selectable parallel Interfaces are 68000-series and 8080-series. They are both an 8-bits bi- directional link between the display driver and the application supervisor. Throughout both parallel interfaces can be read the I 4.3.1 68000-series ...
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Figure 47. 68000-series Parallel interface protocol in Reading Mode Figure 48. 68000-series Parallel interface protocol in Reading Mode (Several Bytes) CS D/C R Note 1) Data Bus is configured in high impedence mode after evry RD ...
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STE2004 Figure 50. 8080-series parallel bus protocol - several bytes transmission CS D Figure 51. 8080-series Parallel interface protocol in Reading Mode Figure 52. 8080-series Parallel interface protocol in Reading Mode (Several Bytes) CS D/C ...
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INSTRUCTION SET Two different instructions formats are provided: - With D/C set to LOW : commands are sent to the Control circuitry. - With D/C set to HIGH : the Data RAM is addressed. Two different instruction set are ...
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STE2004 No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock). The start of Checker-board procedure will be between one and two fclock cycles from the last active edge (E falling edge for the parallel ...
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Figure 53. Dual Partial Display Enabling Instruction Flow Figure 54. Dual Partial Display Mode configuration or Duty Change Table 9. Partial Display Configurations PDC PDC PDC SECTION ...
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STE2004 6 ID-NUMBER The STE2004 allows to program a Driver Identification Number (ID-Number). This make possible to easily manage on one platform more than one LCD module with different configuration parameters. Four are the device ID-Numbers programmable: 00111100, 00111101, 0011110 ...
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Table 11. Extended Instruction Set Instruction D/C R/W Read Command Status Byte Code 0 1 Write Data 1 0 Memory Blank 0 0 Scroll Range Setting 0 0 LCD Display ...
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STE2004 Table 12. Explanations of Table 3 & 4 symbols BIT 0 DIR Scroll by one down H[0] Select page 0 PD Device fully working V Horizontal addressing MX Normal X axis addressing MY Image is displayed not vertically mirrored ...
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Table 17. MULTIPLEXING RATIO M[1] M[ Table 18. TEMPERATURE COEFFICIENT ...
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STE2004 Table 21. BIAS RATIO BS2 BS1 BS0 Table 22. Y CARRIAGE RETURN REGISTER Y-C[3] Y-C[2] ...
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Figure 55. I2C Interface Interconnection in Master/ Slave Mode STE2004 RES SCL RES SCL Figure 56. I3-lines SPI & 3-lines Serial Interfaces Interconnection in Master Slave Mode RES RES MASTER Figure 57. 4-lines SPI Interface Interconnection in Master Slave Mode ...
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STE2004 Figure 58. 8080-series & 68000-series Interface Interconnection in Master Slave Mode STE2004 RES CS RES MASTER CS Figure 59. Host Processor Interconnection with I2C Interface STE2004 46/66 RW-RD D7-D0 D/C E-WR RES 8 LINES D/C RW-RD E-WR D7-D0 SLAVE ...
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Figure 60. Host Processor Interconnection with 4-line SPI Interface STE2004 Figure 61. Host Processor Interconnection with 3-line SPI Interface STE2004 VSS TEST_MODE P VSSAUX SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX ...
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STE2004 Figure 62. Host Processor Interconnection with 3-line Serial Interface STE2004 Figure 63. Host Processor Interconnection with 8080-series Parallel Interface STE2004 48/66 VSS TEST_MODE P VSSAUX SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E ...
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Figure 64. Host Processor Interconnection with 6800 STE2004 VSS TEST_MODE P VSSAUX SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX R D/C CS RES VDD2 ANALOG VDD VDD1 DIGITAL VDD ...
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STE2004 Figure 65. Application Schematic using the Internal LCD Voltage Generator and two separate supplies V DD2 Figure 66. Application Schematic using the Internal LCD Voltage Generator and a single supply ...
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Figure 67. Power-ON timing diagram VDD2 VDD1 RES CS SCLK SDIN D HOST DRIVER SCL- SDAIN SDOUT - SDA OUT OSCIN, FR_IN (HOST) OSC OUT, FR_OUT (DRIVER vdd Tw(res) logic(res) ...
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STE2004 Figure 68. Power-OFF timing diagram VDD2 VDD1 RES CLK-SCL SDIN-SDAIN D R HOST DRIVER SDOUT SDA-OUT OSCIN (HOST) OSC OUT FR_OUT (DRIVER) FR_IN 52/66 T VDD Hi-Z Hi-Z RESET TABLE LOADED ...
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Figure 69. Initialization with built-in Booster SETUP NORMAL DISPLAY MODE CONFIGURATION SET Driver in Power Down(PD=1) SET Driver in Normal Display Mode (PE=0) SET Operative Voltage for Normal Display Operation ( Vop[6:0] - PRS[1;0]) SET Bias Raio for Normal Display ...
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STE2004 Figure 70. DATA RAM to display Mapping DISPLAY DATA RAM bank 0 bank 1 bank 2 bank 3 bank 7 bank 8 Table 25. Test Pin Configuration Test Pin TEST_VREF TEST_MODE 54/66 LCD ICOR ROW D00IN1155 Pin Configuration OPEN ...
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Table 26. Absolute Maximum Ratings Symbol V Supply Voltage Range DD1 V Supply Voltage Range DD2 V LCD Supply Voltage Range LCD I Supply Current SS V Input Voltage (all input pads Input Current ...
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STE2004 Table 23 Electrical Characteristics (continued) DC OPERATION (continued 1 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4 Tamb =-40 to 85°C; unless otherwise specified) DD1 DD2 Symbol ...
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Table 23 Electrical Characteristics (continued) AC OPERATION (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4 Tamb =-40 to 85°C; unless otherwise specified) Symbol Parameter INTERNAL OSCILLATOR F ...
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STE2004 Table 23 Electrical Characteristics (continued) AC OPERATION (continued) (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4 Tamb =-40 to 85°C; unless otherwise specified) Symbol Parameter 2 ...
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Table 23 Electrical Characteristics (continued) AC OPERATION (continued) (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5V; Vss1,2 = 0V; VLCD = 4 Tamb =-40 to 85°C; unless otherwise specified) Symbol Parameter PARALLEL INTERFACE T ...
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STE2004 Table 23 Electrical Characteristics (continued) AC OPERATION (continued) (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4 Tamb =-40 to 85°C; unless otherwise specified) Symbol Parameter SERIAL ...
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Table 28. Pad Coordinates NAME PAD -2925 -2875 -2825 -2775 -2725 -2675 -2625 -2575 -2525 -2475.0 C4 ...
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STE2004 Table 28. Pad Coordinates (continued) NAME PAD C56 63 375.0 C57 64 425.0 C58 65 475.0 C59 66 525.0 C60 67 575.0 C61 68 625.0 C62 69 675.0 C63 70 725.0 C64 71 775.0 C65 72 ...
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Table 28. Pad Coordinates (continued) NAME PAD R48 125 3086.5 R49 126 3086.5 R50 127 3086.5 R51 128 3086.5 R52 129 3086.5 R53 130 3086.5 R54 131 3086.5 R55 132 3086.5 R56 133 3086.5 R57 134 3086.5 ...
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STE2004 Table 28. Pad Coordinates (continued) NAME PAD 187 -675.0 D1 188 -725.0 D0 189 -775.0 VSSAUX 190 -825.0 TEST_MODE 191 -1225.0 VSS 192 -1275.0 VSS 193 -1325.0 VSS 194 -1375.0 VSS 195 -1425.0 VSS 196 ...
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Figure 76. Alignment marks dimensions 94 m Table 32. Revision History Date Revision May 2004 July 2004 Table 30. Bumps Bumps Size Pad Size Pad Pitch 39 m Spacing between Bumps Table 31. Die Mechanical Dimensions Die Size (X x ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...