HY27US08561A Hynix Semiconductor, HY27US08561A Datasheet

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Document Title 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. 1) Change AC Parameter Before 50+tr(R/B#) 0.1 After 60+tr(R/B#) 2) Change 256Mb Package Type. - WSOP package is changed to USOP package. - Figure ...

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Revision History Revision No. 8) Correct PKG dimension (TSOP, USOP PKG) CP Before 0.050 After 0.100 9) Change VIL parameter (max.) Before After 0.2 10) Change AC Parameter Before After tR (1.8V) Before After 0.3 1) Correct USOP figure. 0.4 ...

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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC = ...

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... This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up, Read ID2 extension. The Hynix HY27(U/S)S(08/16)561A series is available TSOP1 USOP1 mm, FBGA mm. 1.1 Product List PART NUMBER HY27SS08561A HY27SS16561A HY27US08561A HY27US16561A Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash ORIZATION VCC RANGE x8 1.70 - 1.95 Volt ...

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IO15 - IO8 IO7 - IO0 CLE ALE R/B Vcc Vss NC PRE Rev 0.5 / Jun. 2006 HY27US(08/16)561A Series HY27SS(08/16)561A Series 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs (x16 ...

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Figure 2. 48TSOP1 Contactions, x8 and x16 Device Figure 3. 48USOP1 Contactions, x8 and x16 Device Rev 0.5 / Jun. 2006 HY27US(08/16)561A Series HY27SS(08/16)561A Series 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash 6 ...

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Figure 4. 63FBGA Contactions, x8 Device (Top view through package) Figure 5. 63FBGA Contactions, x16 Device (Top view through package) Rev 0.5 / Jun. 2006 HY27US(08/16)561A Series HY27SS(08/16)561A Series 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash 7 ...

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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable (WE). ...

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IO0 1st Cycle A0 2nd Cycle A9 3rd Cycle A17 NOTE set to LOW or High by the 00h or 01h Command. IO0 1st Cycle A0 2nd Cycle A9 3rd Cycle A17 NOTE must be ...

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CLE ALE ( NOTE: 1. With ...

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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...

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DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with followed by the three address input cycles. Once the ...

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Block Erase. The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block address loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block ...

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Read Status Register. The device contains a Status Register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or erase operation is completed successfully. After writing 70h command ...

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OTHER FEATURES 4.1 Data Protection & Power On/Off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 2V(3.3V device). WP ...

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Unlock - Command Sequence: Unlock block Command (23h) + Start block address + Command (24h) + End block address. See Fig. 21. - Unlocked blocks can be programmed or erased unlocked block’s status can be changed to ...

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Parameter Symbol Valid Block Number NOTE: 1. The 1st block is guaranteed valid block cycles without ECC. (1bit/512bytes) Symbol Ambient Operating Temperature (Commercial Temperature Range) T Ambient Operating Temperature (Extended Temperature Range) A Ambient ...

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Rev 0.5 / Jun. 2006 HY27US(08/16)561A Series HY27SS(08/16)561A Series 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Figure 6: Block Diagram 18 ...

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Parameter Symbol Sequential I CC1 Read Operating Current Program I CC2 Erase I CC3 Stand-by Current (TTL) I CC4 Stand-by Current (CMOS) I CC5 Input Leakage Current I LI Output Leakage Current I LO Input High Voltage V IH Input ...

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Item Input / Output Capacitance Input Capacitance Table 10: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Program Time Dummy Busy Time for the Lock or Lock-tight Block Number of partial Program Cycles in the same page Block Erase Time Table 11: Program ...

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Parameter CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Data Transfer from Cell to ...

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... Program 0 Pass / Fail Ready/Busy 6 Ready/Busy 7 Write Protect DEVICE IDENTIFIER CYCLE 1st 2nd Part Number HY27US08561A HY27US16561A HY27SS08561A HY27SS16561A Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Block Read Erase Pass / Fail Ready/Busy Ready/Busy ...

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Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Table 16: Lock Status Code Figure 7: Command Latch Cycle HY27US(08/16)561A Series HY27SS(08/16)561A Series 23 ...

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Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Figure 8: Address Latch Cycle HY27US(08/16)561A Series HY27SS(08/16)561A Series 24 ...

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CE RE I/Ox R/B NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. Figure 10: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Rev 0.5 / Jun. 2006 256Mbit ...

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CLE I/O 0-7 CLE CE tWC WE ALE RE I/O 0~7 00h or 01h Col. add 1 Column Address R/B Figure 12: Read1 Operation (Read One Page) Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND ...

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CLE CE WE ALE RE I/O 0~7 00h or 01h Col. add 1 Column Address R/B Figure 13: Read1 Operation intercepted by CE CLE CE WE ALE RE I/O0~7 50h Col. add 1 R/B M Address A0-A3: Valid Address A4-A7: ...

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CLE CE WE ALE RE 00h Col. add1 Row add1 Row add2 I/O0~7 R/B M Figure 15: Sequential Row Read Operation Within a Block Rev 0.5 / Jun. 2006 HY27US(08/16)561A Series HY27SS(08/16)561A Series 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Dout ...

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CLE CE tWC WE ALE RE I/Ox Col. Add1 80h Row Add1 Row Add2 Serial Data Column Input Command Address R/B Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash tWC tWC Din Din N M Row 1 ...

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Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Figure 17 : Copy Back Program HY27US(08/16)561A Series HY27SS(08/16)561A Series 30 ...

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Figure 18: Block Erase Operation (Erase One Block) Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Figure 19: Read ID Operation HY27US(08/16)561A Series HY27SS(08/16)561A Series 31 ...

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Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Figure 20: Lock Command Figure 21: Unlock Command Sequence HY27US(08/16)561A Series HY27SS(08/16)561A Series 32 ...

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Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Figure 22: Lock Tight Command Figure 23: Lock Status Read Timing HY27US(08/16)561A Series HY27SS(08/16)561A Series 33 ...

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WE ALE CLE RE IO7:0 FFh R/B Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Figure 24: Automatic Power at Power On t RST Figure 25: Reset Operation HY27US(08/16)561A Series HY27SS(08/16)561A Series 34 ...

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VTH = 1.5 Volt for 1.8 Volt Supply devices; 2.5 Volt for 3.3 Volt Supply devices Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Figure 26: Power On / Off Timing HY27US(08/16)561A Series HY27SS(08/16)561A Series 35 ...

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Figure 27: Ready/Busy Pin electrical specifications Rev 0.5 / Jun. 2006 HY27US(08/16)561A Series HY27SS(08/16)561A Series 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash 36 ...

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Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Figure 28: Lock/Unlock FSM Flow Cart Figure 29: Pointer operations HY27US(08/16)561A Series HY27SS(08/16)561A Series 37 ...

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Figure 30: Pointer Operations for porgramming Rev 0.5 / Jun. 2006 HY27US(08/16)561A Series HY27SS(08/16)561A Series 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash 38 ...

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System Interface Using CE don’t care To simplify system interface, CE may be inactive during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microprocessor. The only function that was removed ...

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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...

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Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 34~37) Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash ...

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Rev 0.5 / Jun. 2006 HY27US(08/16)561A Series HY27SS(08/16)561A Series 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Figure 36: Enable Erasing Figure 37: Disable Erasing 42 ...

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Figure 38: 48pin-TSOP1 20mm, Package Outline Symbol alpha Table 18: 48pin-TSOP1 20mm, Package Mechanical Data Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND ...

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Figure 39. 48pin-USOP1 17mm, Package Outline Symbol alpha Table 19: 48pin-USOP1 17mm, Package Mechanical Data Rev 0.5 / Jun. 2006 HY27US(08/16)561A Series HY27SS(08/16)561A Series 256Mbit ...

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NOTE: Drawing is not to scale. Symbol FD1 FE FE1 SD SE Table 20: 63ball-FBGA, Pakage Mechanical Data Rev 0.5 / Jun. 2006 256Mbit (32Mx8bit / 16Mx16bit) NAND ...

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MARKING INFORMATION - ...

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MARKING INFORMATION - ...