HY27UG088G5B Hynix Semiconductor, HY27UG088G5B Datasheet

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NAND FLASH HY27UG088G(5/D)B This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B ...

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Document Title 8Gbit (1Gx8bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. 1) Correct Read Cache figure 0.1 2) Add ULGA package 3) Correct Block erase 0.2 1) Delete Preliminary Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit ...

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... Simple interface with microcontroller HARDWARE DATA PROTECTION - Program/Erase locked during Power transitions. DATA RETENTION - 100,000 Program/Erase cycles (with 1bit/528byte ECC years Data Retention PACKAGE - HY27UG088G5B-T(P) : 48-Pin TSOP1 ( 1.2 mm) - HY27UG088G5B-T (Lead) - HY27UG088G5B-TP (Lead Free) - HY27UG088GDB-UP : 52-ULGA ( 0.65 mm) - HY27UG088GDB-UP (Lead Free) 3 ...

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... CE transitions do not stop the read operation. This device includes also extra features like OTP/Unique ID area, Read ID2 extension. The HY27UG088G(5/D)B Series are available in 48-TSOP1 mm, 52-ULGA 12 x 17mm. 1.1 Product List PART NUMBER HY27UG088G5B HY27UG088GDB Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash ...

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IO7 - IO0 CLE ALE CE1, CE2 R/B1, R/B2 Vcc Vss NC Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs Command latch enable Address latch enable Chip ...

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Rev 0.2 / Jan. 2008 Figure 2. 48TSOP1 Contact, x8 Device HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 6 ...

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Figure 3: 52-ULGA Contactions, x8 Device, Dual interface Rev 0.2 / Jan. 2008 (Top view through package) HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 7 ...

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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program IO0-IO7 operations. The inputs are latched on the rising edge of Write Enable (WE). The ...

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IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A12 4th Cycle A20 5th Cycle A28 NOTE must be set to Low. FUNCTION READ1 READ FOR COPY-BACK READ ID RESET PAGE PROGRAM COPY BACK PGM MULTI PLANE PROGRAM ...

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CLE ALE ( NOTE: 1. With ...

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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 3ns on Chip Enable, Write Enable and Read Enable ...

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DEVICE OPERATION 3.1 Page Read. This operation is operated by writing 00h and 30h to the command register along with five address cycles. Two types of operations are available: random read, serial page read. The random read mode is ...

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Multi Plane Program. Device supports multiple plane program possible to program in parallel 2 pages, one per each plane. A multiple plane program cycle consists of a double serial data loading period in which up to 4224bytes ...

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Copy-back Program Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, ...

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EDC Operation Error Detection Code check automatically starts immediately after device becomes busy for a copy back program opera- tion (both single and multiple plane). In the x8 version EDC allows detection of 1 single bit error every 528 ...

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Cache Read Cache read operation allows automatic download of consecutive pages. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page is at page start (A<10:0>=00h), ...

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OTHER FEATURES 4.1 Data Protection & Power On/Off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2.0V(3.3V device). WP pin provides ...

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Parameter Symbol Valid Block NVB Number NOTE: 1. The 1st block is guaranteed valid block at the time of shipment. 2. The number of valid blocks is for single plane & multi-plane operations. 3. Each chip has ...

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Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash Figure 4: Block Diagram 19 ...

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Parameter Sequential Read Operating Current Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (R/B) Table 8: DC ...

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Item Input / Output Capacitance Input Capacitance Table 10: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Program Time / Multi-Plane Program Time Dummy Busy Time for Two Plane Program Number of partial Program Cycles in the same page Block Erase Time / ...

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Parameter CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Data Transfer from Cell to ...

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IO Page Program 0 Pass / Fail Ready / Busy 6 Ready / Busy 7 Write Protect DEVICE IDENTIFIER CYCLE 1st 2nd 3rd 4th 5th Part Number Voltage HY27UG088G(5/D)B 3.3V Rev ...

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Description 1 2 Die / Package Level Cell 4 Level Cell Cell Type 8 Level Cell 16 Level Cell 1 Number of 2 Simultaneously 4 Programmed Pages 8 Interleave Program Not Between Multiple chips Supported Not Write ...

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Description 1 2 Plane Number 4 8 64Mb 128Mb 256Mb 512Mb Plane Size (w/o redundant Area) 1Gb 2Gb 4Gb 8Gb Reserved Table 18: 5rd Byte of Device Idendifier Description Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash ...

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Table 19: Page organization in EDC units (x8 Rev 0.2 / Jan. 2008 Copy back Program Pass/Fail EDC status EDC Validity NA NA Ready/Busy Ready/Busy Write Protect Protected: ‘0’ Not Protected: ...

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Rev 0.2 / Jan. 2008 Figure 5: Command Latch Cycle Figure 6: Address Latch Cycle HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 27 ...

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Rev 0.2 / Jan. 2008 Figure 7: Input Data Latch Cycle HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 28 ...

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Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Figure 9: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L) Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 29 ...

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Figure 11: Read1 Operation (Read One Page) Rev 0.2 / Jan. 2008 Figure 10: Status Read Cycle HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 30 ...

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Figure 12: Read1 Operation intercepted by CE Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 31 ...

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Rev 0.2 / Jan. 2008 Figure 13: Random Data output HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 32 ...

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Figure 14: Read Operation with Read Cache Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 33 ...

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Rev 0.2 / Jan. 2008 Figure 15: Page Program Operation HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 34 ...

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Rev 0.2 / Jan. 2008 Figure 16: Random Data In HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 35 ...

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Rev 0.2 / Jan. 2008 Figure 17: Copy Back Program Operation HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 36 ...

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Figure 18: Copy Back Program Operation with Random Data Input Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 37 ...

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Figure 19: Block Erase Operation (Erase One Block) Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 38 ...

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Rev 0.2 / Jan. 2008 Figure 20: Multiple plane page program HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 39 ...

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Figure 21: Multiple plane erase operation Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 40 ...

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Figure 22: Multi plane copyback program Operation Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 1 41 ...

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Rev 0.2 / Jan. 2008 Figure 23: Read ID Operation HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 42 ...

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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microporcessor. The only function that was removed ...

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Figure 27: Power On and Data Protection Timing Rev 0.2 / Jan. 2008 Figure 26: Reset Operation VTH = 2.5 Volt for 3.3 Volt Supply devices HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 44 ...

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Figure 28: Ready/Busy Pin electrical specifications Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 45 ...

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Figure 29: page programming within a block Rev 0.2 / Jan. 2008 HY27UG088G(5/D)B Series 8Gbit (1Gx8bit) NAND Flash 46 ...

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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...

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Bad Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts ...

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Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 32~35) Rev 0.2 / Jan. 2008 Figure 32: Enable Programming Figure 33: ...

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Rev 0.2 / Jan. 2008 8Gbit (1Gx8bit) NAND Flash Figure 34: Enable Erasing Figure 35: Disable Erasing HY27UG088G(5/D)B Series 50 ...

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Figure 36: 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Symbol alpha Table 22: 48-TSOP1 - 48-lead Plastic Thin Small Outline, Rev 0.2 / Jan. ...

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Figure 37. 51-ULGA 17mm, Package Outline Symbol CP1 CP2 Table 23: 52-ULGA 17mm, Package Mechanical Data Rev 0.2 / Jan. 2008 8Gbit (1Gx8bit) NAND ...

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MARKING INFORMATION - ...