HY27UG088G5M Hynix Semiconductor, HY27UG088G5M Datasheet
HY27UG088G5M
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HY27UG088G5M Summary of contents
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... NAND FLASH This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.6 / Dec. 2006 HY27UG088G5M HY27UG088GDM HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 1 ...
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... Document Title 8Gbit (1Gx8bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. 1) Add HY27UG088G5M & HY27UG088GDM Products. - Texts & figures are added. 2) Change Ac Characteristics tR Before 20 After 25 tCLS Before 12 0.1 After 15 3) Add tCRRH (100ns, Min) - tCRRH: cache Read RE High 4) Change 3rd Read ID - 3rd Read ID is changed to C1h - 3rd Byte of Device Identifier Table is added ...
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Revision History Revision No. 1) Correct Read ID naming 2) Add ECC algorithm. (1bit/512bytes) 3) Change valid block number (max) valid block number Before After 4) Change NOP 0.3 5) Change DC characterics I CC1 Typ Before 25 After 15 ...
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... Simple interface with microcontroller SERIAL NUMBER OPTION HARDWARE DATA PROTECTION - Program/Erase locked during Power transitions DATA INTEGRITY - 100,000 Program/Erase cycles (with 1bit/512byte ECC years Data Retention PACKAGE - HY27UG088G5M-T(P) : 48-Pin TSOP1 ( 1.2 mm) - HY27UG088G5M-T (Lead) - HY27UG088G5M-TP (Lead Free) - HY27UG088GDM-UP :52- ULGA ( 0.65 mm) - HY27UG088GDM-DP (Lead Free) 4 ...
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... This device includes also extra features like OTP/Unique ID area, Read ID2 extension. The HYNIX HY27UG088G(5/D)M series is available TSOP1 mm, 52-ULGA mm. 1.1 Product List PART NUMBER HY27UG088G5M HY27UG088GDM Rev. 0.6 / Dec. 2006 ORIZATION VCC RANGE x8 2 ...
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IO7 - IO0 CLE ALE R/B Vcc Vss NC Rev. 0.6 / Dec. 2006 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs Command latch enable Address latch enable Chip Enable Read ...
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Figure 2. 48TSOP1 Contactions, x8 Device (2CE) Rev. 0.6 / Dec. 2006 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 7 ...
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Figure 3. 52-ULGA Contactions, x8 Device, Dual interface Rev. 0.6 / Dec. 2006 (Top view through package) HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 8 ...
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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program IO0-IO7 operations. The inputs are latched on the rising edge of Write Enable (WE). The ...
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IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A12 4th Cycle A20 5th Cycle A28 NOTE must be set to Low. FUNCTION READ 1 READ FOR COPY-BACK READ ID RESET PAGE PROGRAM (start) COPY BACK PGM (start) ...
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CLE ALE ( NOTE: 1. With ...
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... Write Protect pin is not latched by Write Enable to ensure the pro- tection even during the power up. 2.6 Standby. In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. NOTE addresses are needed to access HY27UG088G5M & HY27UG088GDM. Rev. 0.6 / Dec. 2006 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash (1) ...
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DEVICE OPERATION 3.1 Page Read. Page read operation is initiated by writing 00h and 30h to the command register along with five address cycles. In two consecutive read operations, the second one doesn’t’ need 00h command, which five address ...
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Block Erase. The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command (60h). Only address A18 to A29 (X8) is valid while A12 to A17 (X8) ...
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Copy-Back Program. The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system per- formance is ...
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Read Status Register. The device contains a Status Register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or erase operation is completed successfully. After writing 70h command ...
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Cache Program. Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may ...
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Cache Read Cache read operation allows automatic download of consecutive pages the whole device. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page ...
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OTHER FEATURES 4.1 Data Protection & Power on/off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides ...
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Parameter Symbol Valid Block Number NOTE: 1. The 1st block is guaranteed valid block cycles with ECC. (1bit/512bytes) Symbol Ambient Operating Temperature (Commercial Temperature Range) T Ambient Operating Temperature (Extended Temperature Range) A Ambient ...
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Rev. 0.6 / Dec. 2006 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash Figure 4: Block Diagram 21 ...
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Parameter Sequential Read Operating Current Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (R/B) Table 8: DC ...
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... Program Time Dummy Busy Time for Cache Program Dummy Busy Time for Cache Read Number of partial Program Cycles in the same page Block Erase Time Table 11: Program / Erase Characteristics Rev. 0.6 / Dec. 2006 Test Min Condition HY27UG088G5M-T( Main Array Spare Array ...
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Parameter CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Address to Data Loading Time ...
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... Ready/Busy Ready/Busy 6 Ready/Busy Ready/Busy 7 Write Protect Write Protect DEVICE IDENTIFIER CYCLE 1st 2nd 3rd 4th Part Number Voltage HY27UG088G5M 3.3V HY27UG088GDM 3.3V Rev. 0.6 / Dec. 2006 Cache Read Program Pass / Fail (N) NA Pass / Fail (N- P/E/R Ready/Busy Controller Bit Cache Register ...
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Description 1 2 Internal Chip Number Level Cell 4 Level Cell Cell Type 8 Level Cell 16 Level Cell 1 Number of 2 Simultaneously 4 Programmed Pages 8 Interleave Program Not Support Between multiple chips Support Not ...
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Rev. 0.6 / Dec. 2006 Figure 5: Command Latch Cycle Figure 6: Address Latch Cycle HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 27 ...
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Rev. 0.6 / Dec. 2006 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash Figure 7. Input Data Latch Cycle 28 ...
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Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Figure 9: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L) Rev. 0.6 / Dec. 2006 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 29 ...
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Figure 11: Read1 Operation (Read One Page) Rev. 0.6 / Dec. 2006 Figure 10: Status Read Cycle HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 30 ...
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Figure 12: Read1 Operation intercepted by CE Rev. 0.6 / Dec. 2006 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 31 ...
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Rev. 0.6 / Dec. 2006 Figure 13 : Random Data output HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 32 ...
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Rev. 0.6 / Dec. 2006 Figure 14: Page Program Operation HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 33 ...
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Rev. 0.6 / Dec. 2006 Figure 15 : Random Data In HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 34 ...
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Rev. 0.6 / Dec. 2006 Figure 16 : Copy Back Program HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 35 ...
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Rev. 0.6 / Dec. 2006 Figure 17: Cache Read RE high HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 36 ...
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Rev. 0.6 / Dec. 2006 8Gbit (1Gx8bit) NAND Flash Figure 18 : Cache Program HY27UG088G(5/D)M Series 37 ...
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Figure19: Block Erase Operation (Erase One Block) Rev. 0.6 / Dec. 2006 Figure 20: Read ID Operation HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 38 ...
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Figure 21: start address at page start :after 1st latency uninterrupted data flow Figure 22: exit from cache read in 5us when device internally is reading Rev. 0.6 / Dec. 2006 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 39 ...
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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microporcessor. The only function that was removed ...
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Figure 26: Power On and Data Protection Timing Rev. 0.6 / Dec. 2006 Figure 25: Reset Operation VTH = 2.5 Volt for 3.3 Volt Supply devices HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 41 ...
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Figure 27: Ready/Busy Pin electrical specifications Rev. 0.6 / Dec. 2006 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 42 ...
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Figure 28 : page programming within a block Rev. 0.6 / Dec. 2006 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 43 ...
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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...
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Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 30~33) Rev. 0.6 / Dec. 2006 Figure 30: Enable Programming Figure 31: ...
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Rev. 0.6 / Dec. 2006 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash Figure 32: Enable Erasing Figure 33: Disable Erasing 46 ...
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APPENDIX : Extra Features 5.1 Addressing for program operation Within a block, the pages must be programmed consecutively from LSB (least significant bit) page of the block to MSB (most significant bit) page of the block. Random address programming ...
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Figure 34. 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Symbol alpha Table 19: 48-TSOP1 - 48-lead Plastic Thin Small Outline, Rev. 0.6 / Dec. ...
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Figure 35. 51-ULGA 17mm, Package Outline Symbol CP1 CP2 Table 20: 52-ULGA 17mm, Package Mechanical Data Rev. 0.6 / Dec. 2006 (Top view through ...
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MARKING INFORMATION ...