HY27UH08AG5B Hynix Semiconductor, HY27UH08AG5B Datasheet
HY27UH08AG5B
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HY27UH08AG5B Summary of contents
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... NAND FLASH This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.2 / Jan. 2008 HY27UH08AG5B HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 1 ...
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... NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. 1) Correct Cache Read figure 0.1 2) Correct Block Erase 3) Correct Multiplane operation 0.2 1) Delete Preliminary Rev 0.2 / Jan. 2008 16Gbit (2Gx8bit) NAND Flash History HY27UH08AG5B Series Draft Date Remark Jun. 22. 2007 Preliminary Jun. 27. 2007 Preliminary Jan. 16. 2007 2 ...
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... Multiplane information CHIP ENABLE DON’T CARE - Simple interface with microcontroller HARDWARE DATA PROTECTION - Program/Erase locked during Power transitions. DATA RETENTION - 100,000 Program/Erase cycles (with 1bit/528byte ECC years Data Retention PACKAGE - HY27UH08AG5B-T(P) : 48-Pin TSOP1 ( 1.2 mm) - HY27UH08AG5B-T (Lead) - HY27UH08AG5B-TP (Lead Free) 3 ...
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... DESCRIPTION Hynix NAND HY27UH08AG5B Series have 2048Mx8bit with spare 64Mx8 bit capacity. The device is offered in 3.3 Vcc Power Supply, and with x8 I/O interface Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently possible to preserve valid data while old data is erased ...
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... WE WP R/B1, R/B2 Vcc Vss NC Rev 0.2 / Jan. 2008 16Gbit (2Gx8bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy Power Supply Ground No Connection Table 1: Signal Names HY27UH08AG5B Series 5 ...
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... Rev 0.2 / Jan. 2008 Figure 2. 48TSOP1 Contact, x8 Device HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 6 ...
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... The PCB track widths must be sufficient to carry the currents required during program and erase operations internal voltage detector disables all functions whenever VCC is below 1.8V (3.3V version) or 1.1V (1.8V) version to protect the device from any involuntary program/erase during power transitions. Rev 0.2 / Jan. 2008 16Gbit (2Gx8bit) NAND Flash Description Table 2: Pin Description HY27UH08AG5B Series 7 ...
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... D0h 60h 60h D0h 70h - 85h - 05h E0h 00h 31h 31h - 3Fh - 7Bh - Table 4: Command Set HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash IO4 IO5 IO6 (1) (1) ( A16 A17 A18 A24 A25 A26 (1) (1) (1) L ...
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... 0V/Vcc Table 5: Mode Selection HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash MODE Command Input Read Mode Address Input(5 cycles) Command Input Write Mode Address Input(5 cycles) Data Input Sequential Read and Data Output During Read (Busy) During Program (Busy) ...
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... Write Protect pin is not latched by Write Enable to ensure the protec- tion even during the power up. 2.6 Standby In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 10 ...
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... The command register remains in Read Status command mode until another valid command is written to the com- mand register. Figure 14 details the sequence. Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 11 ...
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... Dummy Busy Time between 1st and 2nd block address insertion. Address limitation required for multiple plane program applies also to multiple plane erase, as well as operation progress can be checked like for mul- tiple plane program. Figure 20 details the sequence Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 12 ...
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... Error Detection Code during copy back operation: thanks to this, 2 bit external ECC is no more required, with signifi- cant advantage for customers that can always use single bit ECC. More details on EDC operation are available in sec- tion 3.8. Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 13 ...
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... If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin goes low for tRST after the Reset command is written. Refer to Figure 25. Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 14 ...
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... The host shall not issue a sequential Read Cache (31h) command after the last page of the device is read. Refer to Figure 13. Cache Read operation must be done only block by block if system needs to avoid reading also reading from invalid blocks. Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 15 ...
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... R/B outputs to be Or-tied. Because pull-up resistor value is related to tR(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with the following reference chart (Fig 27). Its value can be determined by the following guidance. Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 16 ...
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... Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions. Rev 0.2 / Jan. 2008 Min Typ 16064 - Table 6 : Valid Blocks Numbers Parameter Table 7: Absolute maximum ratings HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash Max Unit 16384 Blocks Value - ...
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... Rev 0.2 / Jan. 2008 16Gbit (2Gx8bit) NAND Flash Figure 3: Block Diagram HY27UH08AG5B Series 18 ...
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... Vcc (max Vcc (max) LO OUT =-400uA =2.1mA =0.4V OL (R/B) Table 9: AC Conditions HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 3.3Volt Min Typ Max - 1 200 - - ± ± 40 0.8xVcc - Vcc+0.3 -0.3 - 0.2xVcc 2 ...
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... Block Erase Time / Multi-Plane Block Erase Time Read Cache Busy Time Table 11: Program / Erase Characteristics Rev 0.2 / Jan. 2008 16Gbit (2Gx8bit) NAND Flash Symbol Test Condition C V = Symbol t t NOP t t RCBSY HY27UH08AG5B Series Min Max - Min Typ Max - 200 700 PROG - 0.5 1 DBSY - - 8 - 1.5 2 ...
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... REA t RHZ t CHZ t COH t RHOH t RLOH t REH ADL t WHR t RHW t RST t WW Table 12: AC Timing Characteristics HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 3.3V Min Max 12 CLS ALS ...
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... Internal chip number, cell Type, etc. Page Size, Block Size, Spare Size, Organization Multiplane information Table 14: Device Identifier Coding Bus 1st cycle Width (Manufacture Code) x8 ADh Table 15: Read ID Data Table HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash Cache Read CODING NA Pass: ‘0’ Fail: ‘1’ ...
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... Serial Access Time 25ns Reserved 64K Block Size 128K (Without Spare Area) 256K 512KB X8 Organization X16 Table 17: 4th Byte of Device Identifier Description Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash IO7 IO6 IO5 IO4 IO7 ...
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... Plane Number 4 8 64Mb 128Mb 256Mb 512Mb Plane Size (w/o redundant Area) 1Gb 2Gb 4Gb 8Gb Reserved Table 18: 5rd Byte of Device Idendifier Description Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash IO7 IO6 IO5 IO4 IO3 IO2 ...
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... EDC Validity NA NA Ready/Busy Ready/Busy Write Protect Protected: ‘0’ Not Protected: ‘1’ Table 20: EDC Register Coding HY27UH08AG5B Series CODING Pass: Fail: ‘1’ NO error: ‘0’ Invalid: ‘0’ Valid: ‘1’ Busy: ‘0’ Ready: ‘1’ Busy: ‘0’ Ready: ‘1’ ...
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... Rev 0.2 / Jan. 2008 Figure 4: Command Latch Cycle Figure 5: Address Latch Cycle HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 26 ...
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... Rev 0.2 / Jan. 2008 Figure 6: Input Data Latch Cycle HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 27 ...
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... Figure 7: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Figure 8: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L) Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 28 ...
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... Figure 10: Read1 Operation (Read One Page) Rev 0.2 / Jan. 2008 16Gbit (2Gx8bit) NAND Flash Figure 9: Status Read Cycle HY27UH08AG5B Series 29 ...
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... Figure 11: Read1 Operation intercepted by CE Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 30 ...
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... Rev 0.2 / Jan. 2008 Figure 12: Random Data output HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 31 ...
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... Figure 13: Read Operation with Read Cache Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 32 ...
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... Rev 0.2 / Jan. 2008 Figure 14: Page Program Operation HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 33 ...
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... Rev 0.2 / Jan. 2008 16Gbit (2Gx8bit) NAND Flash Figure 15 : Random Data In HY27UH08AG5B Series 34 ...
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... Rev 0.2 / Jan. 2008 Figure 16: Copy Back Program Operation HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 35 ...
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... Figure 17: Copy Back Program Operation with Random Data Input Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 36 ...
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... Figure 18: Block Erase Operation (Erase One Block) Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 37 ...
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... Rev 0.2 / Jan. 2008 Figure 19: Multiple plane page program HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 38 ...
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... Figure 20: Multiple plane erase operation Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 39 ...
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... Figure 21: Multi plane copyback program Operation Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 1 40 ...
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... Rev 0.2 / Jan. 2008 Figure 22: Read ID Operation HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 41 ...
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... So possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND Flash to make CE don’t care read operation was disabling of the automatic sequential read function. Figure 23: Program Operation with CE don’t-care. Figure 24: Read Operation with CE don’t-care. Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 42 ...
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... Figure 26: Power On and Data Protection Timing Rev 0.2 / Jan. 2008 Figure 25: Reset Operation VTH = 2.5 Volt for 3.3 Volt Supply devices HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 43 ...
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... Figure 27: Ready/Busy Pin electrical specifications Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 44 ...
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... Figure 28: page programming within a block Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 45 ...
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... Figure 29. The 1st block, which is placed on 00h block address is guaranteed valid block. Figure 29: Bad Block Management Flowchart NOTE : 1. Make sure that FFh at the column address 2048 of the 1st page and 2nd page. Rev 0.2 / Jan. 2008 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 46 ...
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... A which is in controller buffer memory is copied into n 4. Bad block table should be updated to prevent from eraseing or programming Block A Rev 0.2 / Jan. 2008 Recommended Procedure ECC (with 1bit/528byte) Table 21: Block Failure Figure 30: Bad Block Replacement HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash Block Replacement Block Replacement th page of Block B 47 ...
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... Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 31~34) Rev 0.2 / Jan. 2008 Figure 31: Enable Programming Figure 32: Disable Programming HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash 48 ...
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... Rev 0.2 / Jan. 2008 16Gbit (2Gx8bit) NAND Flash Figure 33: Enable Erasing Figure 34: Disable Erasing HY27UH08AG5B Series 49 ...
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... Table 22: 48-TSOP1 - 48-lead Plastic Thin Small Outline, Rev 0.2 / Jan. 2008 millimeters Min 0.050 0.980 0.170 0.100 11.910 19.900 18.300 0.500 20mm, Package Mechanical Data HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash Typ Max 1.200 0.150 1.030 0.250 0.200 0.100 12.000 12.120 20.000 20.100 18 ...
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... k(N orm a l Fre ℃ 0℃ ), I(-4 0℃ ℃ (In clu lock ), lock ), ck) : Fixe d Ite -fixe d Ite m HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash ...