MPC875 Freescale Semiconductor, Inc, MPC875 Datasheet

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... This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC875/MPC870. The CPU on the MPC875/MPC870 is a 32-bit core built on Power Architecture™ technology that incorporates memory management units (MMUs) and instruction and data caches. For functional characteristics of the MPC875/MPC870, refer to the MPC885 PowerQUICC™ ...

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... MPC870 8 2 Features The MPC875/MPC870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC875/MPC870 features: • Embedded MPC8xx core up to 133 MHz • ...

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... IEEE 1149.1™ Std. test access port (JTAG) • Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP, IEEE 802.11i® standard, and iSCSI processing. Available on the MPC875, the security engine contains a crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are: — ...

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... Independent (can be connected to SCC or SMC) — Allows changes during operation — Autobaud support option • SCC (serial communication controller) — Ethernet/IEEE 802.3® standard, supporting full 10-Mbps operation — HDLC/SDLC MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev GRACEFUL STOP TRANSMIT ) , ENTER HUNT Freescale Semiconductor ...

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... Serial peripheral interface (SPI) — Supports master and slave modes — Supports multiple-master operation on the same bus • Inter-integrated circuit (I — Supports master and slave modes — Supports a multiple-master environment MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 2 C) port Features 5 ...

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... Features • The MPC875 has a time-slot assigner (TSA) that supports one TDM bus (TDMb) — Allows SCC and SMC to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined — 8-bit resolution — Allows independent transmit and receive routing, frame synchronization, and clocking — ...

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... The MPC875 block diagram is shown in Instruction Instruction Cache Bus Instruction MMU Embedded MPC8xx Processor Core Load/Store Bus Fast Ethernet Controller DMAs DMAs DMAs FIFOs 10/100 BaseT Media Access Control Parallel Interface MIII/RMII MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Figure 1 ...

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... Load/Store Bus 32-Entry DTLB Fast Ethernet Controller DMAs DMAs DMAs FIFOs 10/100 BaseT Media Access Control Parallel Interface MIII/RMII MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Figure 2. 8-Kbyte Unified 32-Entry ITLB Bus 8-Kbyte Data Cache Data MMU Slave/Master IF 4 Interrupt Parallel I/O ...

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... Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than V normal operation (that is, if the MPC875/MPC870 is unpowered, a voltage greater than 2.5 V must not be applied to its inputs). Figure 3 shows the undershoot and overshoot voltages at the interfaces of the MPC875/MPC870. ...

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... Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND Thermal Characteristics Table 4 shows the thermal characteristics for the MPC875/MPC870. Table 4. MPC875/MPC870 Thermal Resistance Data Rating 1 Junction-to-ambient Natural convection ...

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... The V power dissipation is negligible. DDSYN 6 DC Characteristics Table 6 provides the DC electrical characteristics for the MPC875/MPC870. Characteristic Operating voltage Input high voltage (all inputs except EXTAL and EXTCLK) 3 Input low voltage EXTAL, EXTCLK input high voltage Input leakage current ...

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... The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity T MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev 3.0 V (except XTAL and DDH cannot be more than 100 mV ...

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... When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application [2 more accurate and complex model of the package can be used in the thermal simulation. MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor θCA . For instance, the user can change the airflow around θ ...

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... V. This restriction applies to power up, power down, and normal operation. MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev can be used to determine the junction temperature with and PLL voltage (V DDL ). The I/O section of the MPC875/MPC870 is supplied with 3.3 V DDH (415) 964-5111 800-854-7179 or 303-397-7956 http://www.jedec.org ), which both operate at a lower DDSYN Freescale Semiconductor ...

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... Figure 4. Example Voltage Sequencing Circuit 9 Mandatory Reset Configurations The MPC875/MPC870 requires a mandatory configuration during reset. If hardware reset configuration word (HRCW) is enabled, the HRCW[DBGC] value needs to be set to binary X1 in the HRCW and the SIUMCR[DBGC] should be programmed with the same value in the boot code after reset ...

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... GND should be kept to less than half an inch per capacitor lead minimum, a four-layer board employing two inner layers as V All output pins on the MPC875/MPC870 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times ...

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... Bus Signal Timing The maximum bus speed supported by the MPC875/MPC870 is 80 MHz. Higher-speed parts must be operated in half-speed bus mode (for example, an MPC875/MPC870 used at 133 MHz must be configured for a 66 MHz bus). Table 8 shows the frequency ranges for standard part frequencies in 1:1 bus mode, and Table 9 shows the frequency ranges for standard part frequencies in 2:1 bus mode ...

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... PCMCIA interface) (MAX = 0.00 × 9.00) CLKOUT to TS, BB High-Z (MIN = 0.25 × B1) B13 B13a CLKOUT to TA, BI High-Z (when driven by the memory controller or PCMCIA interface) (MIN = 0.00 × 2.5) B14 CLKOUT to TEA assertion (MAX = 0.00 × 9.00) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev MHz 40 MHz Min Max Min Max 12.1 18.2 10.0 15 ...

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... GPCM write access ACS = 00, TRLX = 0 and CSNT = 0 (MAX = 0.00 × 8.00) B24 A(0:31) and BADDR(28:30 asserted GPCM ACS = 10, TRLX = 0 (MIN = 0.25 × B1 – 2.00) B24a A(0:31) and BADDR(28:30 asserted GPCM ACS = 11, TRLX = 0 (MIN = 0.50 × B1 – 2.00) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 33 MHz 40 MHz Min Max Min 2.50 15.00 2.50 6.00 — ...

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... B29b CS negated to D(0:31) High-Z GPCM write access, ACS = 00, TRLX = 0 and CSNT = 0 (MIN = 0.25 × B1 – 2.00) B29c CS negated to D(0:31) High-Z GPCM write access, TRLX = 0, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 (MIN = 0.50 × B1 – 2.00) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev MHz 40 MHz 66 MHz Min Max Min ...

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... B1 – 2.00) B30c WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1 ACS = 10 or ACS == 11, EBDF = 1 (MIN = 0.375 × B1 – 3.00) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 33 MHz 40 MHz Min Max Min Max 43.50 — ...

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... BST1 in the corresponding word in the UPM, EBDF = 1 (MAX = 0.375 × 6.60) B33 CLKOUT falling edge to GPL valid as requested by control bit GxT4 in the corresponding word in the UPM (MAX = 0.00 × 6.00) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev MHz 40 MHz 66 MHz Min Max Min ...

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... B1 + 1.00) B39 AS valid to CLKOUT rising edge (MIN = 0.00 × 7.00) B40 A(0:31), TSIZ(0:1), RD/WR, BURST valid to CLKOUT rising edge (MIN = 0.00 × 7.00) B41 TS valid to CLKOUT rising edge (setup time) (MIN = 0.00 × 7.00) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 33 MHz 40 MHz Min Max Min 7.60 14.30 6.30 5.60 — ...

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... For part speeds above 50 MHz, use 9.80 ns for B11a. 2 The timing required for BR input is relevant when the MPC875/MPC870 is selected to work with the internal bus arbiter. The timing for BG input is relevant when the MPC875/MPC870 is selected to work with the external bus arbiter. 3 For part speeds above 50 MHz, use 2 ns for B17. ...

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... Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 6 provides the timing for the external clock. CLKOUT MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Figure 5. Control Timing B1 ...

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... Figure 7. Synchronous Output Signals Timing Figure 8 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT TS, BB TA, BI TEA Figure 8. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B8a B9 B8b B11 ...

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... It also applies to normal read accesses under the control of the user-programmable machine (UPM) in the memory controller. CLKOUT TA D[0:31] Figure 10. Input Data Timing in Normal Case MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B16 B17 B16a B17a ...

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... Figure 15 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31] Figure 12. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B20 B21 B11 B12 B8 B22 B25 B28 B18 B23 B26 ...

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... CLKOUT TS A[0:31] CSx OE D[0:31] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31] Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B11 B12 B8 B22a B24 B25 B18 B11 B12 B8 B22b B22c B24a ...

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... Bus Signal Timing CLKOUT B11 TS A[0:31] CSx OE D[0:31] Figure 15. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B12 B8 B22a B27 B27a B18 B22b B22c B23 B26 B19 Freescale Semiconductor ...

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... Figure 18 provide the timing for the external bus write controlled by various GPCM factors. CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B11 B12 B8 B22 B25 B26 B8 Bus Signal Timing B30 ...

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... Bus Signal Timing CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B11 B12 B8 B22 B28b B28d B25 B26 B28a B28c B8 B30a B30c B23 B29c B29g B29a B29f B9 Freescale Semiconductor ...

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... CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 18. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B12 B8 B22 B28b B28d B25 B26 B8 Bus Signal Timing B30b B30d B23 B29e B29i B29d B29h B29b B28a B28c B9 33 ...

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... Bus Signal Timing Figure 19 provides the timing for the external bus controlled by the UPM. CLKOUT A[0:31] CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 19. External Bus Timing (UPM Controlled Signals) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B31a B31d B31 B34 B34a B34b B32a B32d ...

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... UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 21. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B38 B38 Bus Signal Timing 35 ...

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... Figure 23. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure 24 provides the timing for the asynchronous external master control signals negation. AS CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 24. Asynchronous External Master—Control Signals Negation Timing MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B41 B42 B40 B39 B40 B43 ...

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... The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have no direct relation with the total system interrupt latency that the MPC875/MPC870 is able to support. Figure 25 provides the interrupt detection timing for the external level-sensitive lines ...

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... Bus Signal Timing Table 12 shows the PCMCIA timing for the MPC875/MPC870. Num Characteristic A(0:31), REG valid to PCMCIA strobe P44 1 (MIN = 0.75 × B1 – 2.00) asserted A(0:31), REG valid to ALE negation P45 (MIN = 1.00 × B1 – 2.00) CLKOUT to REG valid P46 (MAX = 0.25 × 8.00) CLKOUT to REG invalid P47 (MIN = 0.25 × 1.00) ...

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... PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 27. PCMCIA Access Cycles Timing External Bus Read MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor P44 P46 P45 P48 P50 P52 P53 B18 ...

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... PCWE, IOWR ALE D[0:31] Figure 28. PCMCIA Access Cycles Timing External Bus Write Figure 29 provides the PCMCIA WAIT signals detection timing. CLKOUT WAITA Figure 29. PCMCIA WAIT Signals Detection Timing MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev P44 P46 P45 P48 P50 P52 P53 ...

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... PCMCIA output port timing for the MPC875/MPC870. CLKOUT Output Signals HRESET OP2, OP3 Figure 31 provides the PCMCIA input port timing for the MPC875/MPC870. CLKOUT Input Signals MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 13. PCMCIA Port Timing 33 MHz ...

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... Bus Signal Timing Table 14 shows the debug port timing for the MPC875/MPC870. Num Characteristic D61 DSCK cycle time D62 DSCK clock pulse width D63 DSCK rise and fall times D64 DSDI input data setup time D65 DSDI data hold time D66 ...

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... Table 15 shows the reset timing for the MPC875/MPC870. Num Characteristic CLKOUT to HRESET high impedance R69 (MAX = 0.00 × 20.00) CLKOUT to SRESET high impedance R70 (MAX = 0.00 × 20.00) RSTCONF pulse width R71 (MIN = 17.00 × B1) R72 — Configuration data to HRESET rising R73 edge setup time (MIN = 15.00 × 50.00) ...

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... Figure 35. Reset Timing—Data Bus Weak Drive During Configuration Figure 36 provides the reset timing for the debug port configuration. CLKOUT SRESET DSCK, DSDI Figure 36. Reset Timing—Debug Port Configuration MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev R71 R76 R73 R74 R75 ...

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... IEEE 1149.1 Electrical Specifications Table 16 provides the JTAG timings for the MPC875/MPC870 shown in Num J82 TCK cycle time J83 TCK clock pulse width measured at 1.5 V J84 TCK rise and fall times J85 TMS, TDI data setup time J86 TMS, TDI data hold time ...

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... Figure 38. JTAG Test Access Port Timing Diagram TCK TRST TCK Output Signals Output Signals Output Signals Figure 40. Boundary Scan (JTAG) Timing Diagram MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev J85 J86 J87 J88 J91 J90 Figure 39. JTAG TRST Timing Diagram J92 J93 ...

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... SDACK negation delay from clock high 46 TA assertion to rising edge of the clock setup time (applies to external TA) 1 Applies to high-to-low mode (EDM = 1). MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 17. Port C Interrupt Timing Characteristic 35 Figure 41. Port C Interrupt Detection Timing Figure 42 Table 18 ...

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... CPM Electrical Characteristics CLKO (Output) DREQ (Input) Figure 42. IDMA External Requests Timing Diagram CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 43. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

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... CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 44. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 45. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor CPM Electrical Characteristics 45 49 ...

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... Num 61 TIN/TGATE rise and fall time 62 TIN/TGATE low time 63 TIN/TGATE high time 64 TIN/TGATE cycle time 65 CLKO low to TOUT valid MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Table 19. Baud Rate Generator Timing Characteristic Table 20. Timer Timing Characteristic Figure 46. ...

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... L1CLKB edge to L1ST1 and L1ST2 invalid 80 L1CLKB edge to L1TXDB valid 80A L1TSYNCB valid to L1TXDB valid 81 L1CLKB edge to L1TXDB high impedance 82 L1RCLKB, L1TCLKB frequency (DSC = 1) 83 L1RCLKB, L1TCLKB width low (DSC = 1) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 21. SI Timing Characteristic ...

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... L1RCLKB ( (Input) 71 L1RCLKB ( (Input) L1RSYNCB (Input) 73 L1RXDB (Input) L1ST(2–1) (Output) Figure 48. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Table 21. SI Timing (continued) Characteristic 71a 72 RFSD BIT0 76 ...

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... (Input) 82 L1RCLKB ( (Input) 75 L1RSYNCB (Input) 73 L1RXDB (Input) 76 L1ST(2–1) (Output) L1CLKOB (Output) Figure 49. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 72 83a RFSD BIT0 78 84 CPM Electrical Characteristics 79 53 ...

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... CPM Electrical Characteristics L1TCLKB ( (Input) 71 L1TCLKB ( (Input) 73 L1TSYNCB (Input) L1TXDB (Output) L1ST(2–1) (Output) Figure 50. SI Transmit Timing Diagram (DSC = 0) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev TFSD 80a BIT0 Freescale Semiconductor ...

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... L1RCLKB ( (Input) L1RSYNCB (Input) 73 L1TXDB BIT0 (Output) 80 78a L1ST(2–1) (Output) 84 L1CLKOB (Output) Figure 51. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 72 83a 82 TFSD CPM Electrical Characteristics 79 55 ...

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... CPM Electrical Characteristics MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Figure 52. IDL Timing Freescale Semiconductor ...

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... CD3 setup time to RCLK3 rising edge 1 The ratios SYNCCLK/RCLK3 and SYNCCLK/TCLK3 must be greater or equal to 3/1. 2 Also applies to CD and CTS hold time when they are used as external SYNC signals. MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 22. NMSI External Clock Timing Characteristic 1 2 Table 23 ...

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... Figure 53. SCC NMSI Receive Timing Diagram TCLK3 102 TxD3 (Output) RTS3 (Output) CTS3 (Input) CTS3 (SYNC Input) Figure 54. SCC NMSI Transmit Timing Diagram MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev 102 101 100 107 102 101 100 103 105 104 108 ...

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... TXD3 active delay (from TCLK3 rising edge) 132 TXD3 inactive delay (from TCLK3 rising edge) 133 TENA active delay (from TCLK3 rising edge) 134 TENA inactive delay (from TCLK3 rising edge) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 102 101 100 103 104 ...

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... SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. CLSN(CTS1) (Input) Figure 56. Ethernet Collision Timing Diagram RCLK3 RxD3 (Input) RENA(CD3) (Input) Figure 57. Ethernet Receive Timing Diagram MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Table 24. Ethernet Timing (continued) Characteristic 2 2 120 121 124 125 ...

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... SMTXD active delay (from SMCLK falling edge) 154 SMRXD/SMSYNC setup time 155 RXD1/SMSYNC hold time 1 SYNCCLK must be at least twice as fast as SMCLK. MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 128 121 132 Figure Table 25. SMC Transparent Timing Characteristic CPM Electrical Characteristics ...

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... Master data hold time (inputs) 164 Master data valid (after SCK edge) 165 Master data hold time (outputs) 166 Rise time output 167 Fall time output MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev 152 151 151 150 Note 1 154 155 154 ...

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... SPICLK ( (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI msb (Output) Figure 61. SPI Master ( Timing Diagram MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 167 166 160 167 162 166 Data lsb 165 164 166 Data lsb ...

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... SPICLK ( (Input) 177 SPIMISO msb (Output) 175 176 SPIMOSI msb (Input) Figure 62. SPI Slave ( Timing Diagram MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Figure 62 and Table 27. SPI Slave Timing Characteristic 172 182 181 170 181 182 180 Data ...

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... High period of SCL 205 Start condition setup time 206 Start condition hold time 207 Data hold time 208 Data setup time 209 SDL/SCL rise time MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 172 170 182 181 181 182 180 msb Data ...

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... The ratio SYNCCLK/(BRGCLK/pre_scalar) must be greater than or equal to 4/1. 2 Figure 64 shows the I C bus timing. SDA 202 203 205 SCL 206 MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Timing (SCL < 100 kH Z Characteristic 2 Table 29 Timing (SCL > 100 kH Expression fSCL ...

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... MII_RX_CLK pulse width high M4 MII_RX_CLK pulse width low M1_RMII RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK setup M2_RMII RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR hold MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 30 lists the USB interface timings. Characteristic 1 Table 31. MII Receive Signal Timing Characteristic USB Electrical Characteristics ...

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... MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid M7 MII_TX_CLK pulse width high M8 MII_TX_CLK pulse width low M20_RMII RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup M21_RMII RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising edge MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Table 32. MII Transmit Signal Timing Characteristic M4 ...

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... M12 MII_MDIO (input) to MII_MDC rising edge setup M13 MII_MDIO (input) to MII_MDC rising edge hold M14 MII_MDC pulse width high M15 MII_MDC pulse width low MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 33. MII Async Inputs Signal Timing M9 Characteristic FEC Electrical Characteristics ...

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... FEC Electrical Characteristics Figure 68 shows the MII serial management channel timing diagram. MII_MDC (Output) MII_MDIO (Output) MII_MDIO (Input) Figure 68. MII Serial Management Channel Timing Diagram MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev M14 MM15 M10 M11 M12 M13 Freescale Semiconductor ...

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... Mechanical Data and Ordering Information Table 35 identifies the packages and operating frequencies available for the MPC875/MPC870. Table 35. Available MPC875/MPC870 Packages/Frequencies Package Type Plastic ball grid array ZT suffix—Leaded VR suffix—Lead-Free are available as needed Plastic ball grid array CZT suffix—Leaded CVR suffix—Lead-Free are available as needed MPC875/MPC870 PowerQUICC™ ...

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... D13 P D23 D17 PE22 PE25 T PD8 PE26 PA1 U N/C PE20 PE23 MII-TX-EN Figure 69. Pinout of the PBGA Package MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev NOTE NOTE: This is the top view of the device OP0 ALEA IPB0 BURST IRQ6 BR OP1 ...

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... Table 36 contains a list of the MPC875/MPC870 input and output signals and shows multiplexing and pin assignments. Table 36. Pin Assignments Name A[0:31] R16, N14, M14, P15, P17, P16, N15, N16, M15, N17, L14, M16, L15, M17, K14, L16, L17, K17, G17, K15, J16, J15, G16, J14, H17, ...

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... B7 CE1_A C15 CE2_A D14 WAIT_A D4 IP_A0 G6 IP_A1 F5 IP_A2, IOIS16_A D3 IP_A3 E4 IP_A4 D2 IP_A5 E3 MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev JEDEC Standard (continued) — Pin Number Type Output Output Output Output Output Output Output Output Output Output Bidirectional (3.3 V only) Bidirectional Output Input (3.3 V only) Input (3 ...

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... RMII1-CRS_DV, TXD4 PA1, MII1-RXD0, T4 RMII1-RXD0, BRGO4 PA0, MII1-RXD1, P6 RMII1-RXD1, TOUT4 PB31, SPISEL, MII1-TXCLK, T5 RMII1-REFCLK MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information JEDEC Standard (continued) — Pin Number Type Input (3.3 V only) Input (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional (3 ...

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... T10 USBTXP PC6, CD4, L1RSYNCB, P10 USBTXN PD8, RXD4, MII-MDC, T3 RMII-MDC PE31, CLK8, L1TCLKB, P9 MII1-RXCLK PE30, L1RXDB, MII1-RXD2 R8 MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev JEDEC Standard (continued) — Pin Number Type Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional ...

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... RMII2-TXD1 PE14, MII2-TXD0, P8 RMII2-TXD0 TMS T14 TDI, DSDI T13 TCK, DSCK R13 TRST U14 MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information JEDEC Standard (continued) — Pin Number Type Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional ...

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... F7, F8, F9, F10, F11, H6, H13, J6, J13, K6, K13, L6, L13, N7, N8, DDL N9, N10, N11 V G7, G8, G9, G10, G11, G12, H7, H12, J7, J12, K7, K12, L7, L12, M7, DDH M8, M9, M10, M11, M12 N/C B17, T16, U2, U17 MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev JEDEC Standard (continued) — Pin Number Type Output (5-V tolerant) Input ...

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... MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC875/MPC870VRXXX. Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC875/MPC870ZTXXX. Figure 70. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 ...

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... Fixed table formatting. Nontechnical edits. Released to the external web. 1.1 10/2003 Added TDMb to the MPC875 Features list, the MPC875 Block Diagram, added 13.5 Serial Interface AC Electrical Specifications, and removed TDMa from the pin descriptions. 2.0 12/2003 Changed DBGC in the Mandatory Reset Configuration to X1. Changed the maximum operating frequency to 133 MHz. ...

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... Figure • In Table • In Figure MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Changes 5, changed all reference voltage measurement points from 0.2 and 0 50% level. 18, changed num 46 description to read, “TA assertion to rising edge ...” 43, changed TA to reflect the rising edge of the clock. ...

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... Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Document Revision History 83 ...

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... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC875EC Rev. 4 08/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...