MPC875 Freescale Semiconductor, Inc, MPC875 Datasheet - Page 37

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MPC875

Manufacturer Part Number
MPC875
Description
Mpc875 Powerquicc Integrated Communications Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Table 11
1
Figure 25
Figure 26
Freescale Semiconductor
The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as level
sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT.
The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have no direct
relation with the total system interrupt latency that the MPC875/MPC870 is able to support.
Num
I39
I40
I41
I42
I43
provides the interrupt timing for the MPC875/MPC870.
IRQx valid to CLKOUT rising edge (setup time)
IRQx hold time after CLKOUT
IRQx pulse width low
IRQx pulse width high
IRQx edge-to-edge time
provides the interrupt detection timing for the external level-sensitive lines.
provides the interrupt detection timing for the external edge-sensitive lines.
CLKOUT
CLKOUT
IRQx
IRQx
Figure 25. Interrupt Detection Timing for External Level Sensitive Lines
Figure 26. Interrupt Detection Timing for External Edge-Sensitive Lines
MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4
Characteristic
Table 11. Interrupt Timing
1
I43
I39
I41
I40
I43
4 × T
CLOCKOUT
2.00
3.00
3.00
6.00
Min
I42
All Frequencies
Max
Bus Signal Timing
Unit
ns
ns
ns
ns
37

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