MPC875 Freescale Semiconductor, Inc, MPC875 Datasheet - Page 16

• Manufacturer Part Number: MPC875
• Description: Mpc875 Powerquicc Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

Layout Practices
10 Layout Practices
Each V
supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power
supply pins drive distinct groups of logic on chip. The V
using at least four 0.1-µF bypass capacitors located as close as possible to the four sides of the package.
Each board designed should be characterized and additional appropriate decoupling capacitors should be
used if required. The capacitor leads and associated printed-circuit traces connecting to chip V
GND should be kept to less than half an inch per capacitor lead. At a minimum, a four-layer board
employing two inner layers as V
All output pins on the MPC875/MPC870 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections caused by
these fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of 6 inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V
inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For
more information, refer to Section 14.4.3, “Clock Synthesizer Power (V
the MPC885 PowerQUICC™ Family Reference Manual.
16
PADIR (Port A data direction register)
PBPAR (Port B pin assignment register)
PBDIR (Port B data direction register)
PCPAR (Port C pin assignment register)
PCDIR (Port C data direction register)
PDPAR (Port D pin assignment register)
PDDIR (Port D data direction register)
DD
pin on the MPC875/MPC870 should be provided with a low-impedance path to the board’s
Table 7. Mandatory Reset Configuration of MPC875/MPC870 (continued)
MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4
Register/Configuration
DD
DD
and GND planes should be used.
and GND circuits. Pull up all unused inputs or signals that will be
DD
power supply should be bypassed to ground
DDSYN
PADIR[5:9]
PADIR[12:13]
PBPAR[14:18]
PBPAR[20:22]
PBDIR[14:8]
PBDIR[20:22]
PCPAR[4:5]
PCPAR[8:9]
PCPAR[14]
PCDIR[4:5]
PCDIR[8:9]
PCDIR[14]
PDPAR[3:7]
PDPAR[9:5]
PDDIR[3:7]
PDDIR[9:15]
, V
Field
SSSYN
Freescale Semiconductor
, V
SSSYN1
DD
(Binary)
Value
and
),” in
0
0
0
0
0
0
0