PIC16C926 Microchip Technology Inc., PIC16C926 Datasheet - Page 73

• Manufacturer Part Number: PIC16C926
• Description: 64/68-pin Cmos Microcontrollers With Lcd Driver
• Manufacturer: Microchip Technology Inc.

9.3.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
FIGURE 9-17:
9.3.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then, pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 9-18).
FIGURE 9-18:
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
2001 Microchip Technology Inc.
SSPOV (SSPCON<6>)
S
S
A7 A6 A5 A4 A3 A2 A1
1
Reception
Transmission
A7
2
1
Data in
sampled
Receiving Address
3
A6
2
I
I
4
2
2
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
A5
Receiving Address
3
5
A4
4
6
R/W=0
7
A3
5
8
A2
6
ACK
9
A1
7
D7
1
R/W = 1
D6
2
8
SSPBUF register is read
Preliminary
Receiving Data
D5
3
Cleared in software
9
ACK
D4
Bit SSPOV is set because the SSPBUF register is still full.
responds to SSPIF
4
SCL held low
while CPU
D3
5
D2
6
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the mas-
ter-receiver is latched on the rising edge of the ninth
SCL input pulse. If the SDA line was high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset and the
slave then monitors for another occurrence of the
START bit. If the SDA line was low (ACK), the transmit
data must be loaded into the SSPBUF register, which
also
RC3/SCK/SCL should be enabled by setting bit CKP.
D1
7
D7
D0
1
SSPBUF is written in software
8
loads
ACK
9
D6
2
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
D7
Cleared in software
1
D5
3
PIC16C925/926
D6
the
2
D4
4
D5
Receiving Data
3
SSPSR
Transmitting Data
D3
D4
4
5
ACK is not sent.
D3
5
D2
6
D2
6
From SSP Interrupt
Service Routine
D1
7
register.
D1
7
D0
8
D0
DS39544A-page 71
8
ACK
ACK
9
9
Then,
Bus Master
terminates
transfer
P
P
pin