MT9HVF12872PY-667 Micron Semiconductor Products, MT9HVF12872PY-667 Datasheet - Page 11

• Manufacturer Part Number: MT9HVF12872PY-667
• Description: 256mb, 512mb, 1gb X72, Sr 240-pin Ddr2 Sdram Vlp Rdimm
• Manufacturer: Micron Semiconductor Products

Table 12:
PDF: 09005aef81de9391/Source: 09005aef81de9385
HVF9C32_64_128x72.fm - Rev. D 06/08 EN
Parameter/Condition
Operating one bank active-precharge current:
(I
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
(I
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are
switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
=
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads, I
MAX (I
Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads, I
t
is HIGH between valid commands; Address bus inputs are stable during
deselects; Data bus inputs are switching
CK =
CK (I
DD
DD
t
RP (I
),
),
DD
t
t
t
RAS =
RCD =
CK (I
DD
DD
DD
OUT
OUT
),
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus
),
t
RC =
DD
t
= 0mA; BL = 4, CL = CL (I
t
= 0mA; BL = 4, CL = CL (I
RP =
RP =
t
t
RAS MIN (I
DDR2 I
Values shown are for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb
(128 Meg x 8) component data sheet.
RCD (I
); CKE is LOW; Other control and address bus
t
RC (I
DD
t
t
RP (I
RP (I
), AL = 0;
DD
DD
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands;
),
DD
DD
t
); CKE is HIGH, S# is HIGH between valid commands;
); CKE is HIGH, S# is HIGH between valid commands;
CK =
t
Specifications and Conditions (Die Revision A) – 1GB
RRD =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid
t
CK =
t
CK (I
t
256MB, 512MB, 1GB (x72, SR): 240-Pin DDR2 SDRAM VLP RDIMM
RRD (I
t
CK (I
t
DD
DD
DD
CK =
); REFRESH command at every
), AL = 0;
), AL =
DD
DD
t
CK (I
),
),
t
t
RCD =
RC =
t
RCD (I
DD
t
CK =
),
t
t
RC (I
CK =
t
t
RAS =
RCD (I
t
DD
CK =
t
CK =
t
CK (I
) - 1 ×
DD
t
CK (I
DD
t
),
t
t
OUT
CK (I
CK =
RAS MAX (I
t
DD
DD
t
CK (I
t
CK =
11
); CKE is HIGH, S#
RAS =
t
4W
DD
),
CK (I
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
= 0mA;
DD
t
t
),
DD
RAS =
CK (I
t
),
t
CK (I
RAS =
DD
); CKE is
t
t
RAS MIN
t
RC =
RFC (I
);
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
t
t
RAS
CK =
); CKE
),
t
);
t
RAS
RC
t
DD
RP
)
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
Electrical Specifications
1,665
1,710
2,520
3,015
-80E/
-800
900
990
585
630
405
126
675
63
63
©2006 Micron Technology, Inc. All rights reserved.
1,440
1,440
2,340
2,700
-667
810
900
495
540
360
126
630
63
63
1,170
1,305
2,250
2,610
-53E
720
855
369
405
315
126
495
63
63
1,980
2,340
-40E
630
720
315
360
315
126
405
990
990
63
63