TSS463C ATMEL Corporation, TSS463C Datasheet - Page 39

• Manufacturer Part Number: TSS463C
• Description: Van Data Link Controller With Serial Interface
• Manufacturer: ATMEL Corporation

Message Length And Status
Register
M_L [4:0]: Message Length
CHER: Channel Error Status
and Abort Command
CHTx: Channel Transmitted and
Transmit Enable Command
CHRx: Channel Received and
Receive Enable Command
7601B–AUTO–02/06
The message length and status register at address (base_address + 0x03) is also 8 bits
wide. It indicates the length of reserved for the message in the Message DATA RAM
area.
•
The 5 high bits of this register allows the user to specify either the length of the message
to be transmitted, or the maximum length of a message receivable in the pointed recep-
tion buffer.
Note: The first byte in this register does not contain data, but the length of the message
received. This implies that the length value has to be equal to or greater than the maxi-
mum length of a message to be received in this buffer (or the length of a message to be
transmitted) plus 1, thus allowing a maximum length of 30 bytes and a minimum length
of 0 byte.
If the value of this field is “illegal” (i.e 0x00) then this message pointer is defined as
being a link (see Message pointer and register and “Linked Channels” on page 52).
As status, this bit is set by the TSS463C when error occurs in transmission or on a
received frame. The user must reset it.
To abort the transmission defined in the channel, this bit can be set to 1 by the user (see
Section “Activate, Idle and Sleep Modes”, page 51 and “Abort” on page 49)
The 2 low order bits of this register contain the message status. Together with the RNW
and RTR bits of the command register (base_address + 0x01), they define the message
type of this channel (see section “Message Types” on page 44). As a general rule, the
status bits are only set by the TSS463C, so the user must reset them to perform a trans-
mission (CHTx) or/and a reception (CHRx). The received and transmitted bits are only
set if the corresponding frame is without errors or if the retry count has been exceeded.
Note:
M_L 4
Read/Write register.
7
1.
M_L [4:0] = 0x1D
M_L [4:0] = 0x1E
M_L [4:0] = 0x1F
M_L [4:0] = 0x00
M_L [4:0] = 0x01
M_L [4:0] = 0x02
M_L 3
Different of a reply request frame with no in-frame reply (deferred reply).
6
- - - - - - -
M_L 2
5
M_L 1
4
M_L 0
3
CHER
- - - - - - - - - - - - - - - - - - - - - -
Frame with no DATA field
2
Frame with 28 DATA bytes
Frame with 29 DATA bytes
Frame with 30 DATA bytes
Frame with 1 DATA byte
Linked channel
CHTx
1
CHRx
0
TSS463C
(1)
base_address
+ 0x03
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