MACH4-96-96-15 Lattice Semiconductor Corp., MACH4-96-96-15 Datasheet - Page 7

• Manufacturer Part Number: MACH4-96-96-15
• Description: High-performance Ee Cmos Programmable Logic
• Manufacturer: Lattice Semiconductor Corp.

FUNCTIONAL DESCRIPTION
The M4-96/96 consists of six PAL blocks connected by a central switch matrix. There are 96 I/O
pins and 6 dedicated input pins feeding the central switch matrix. These signals are distributed to
the eight PAL blocks for efficient design implementation. There are 4 global clock pins that can
also be used as dedicated inputs.
All inputs and I/O pins have built-in pull-up resistors. While it is always good design practice to
tie unused pins high, the pull-up resistors provide design security and stability in the event that
unused pins are left disconnected.
The PAL Blocks
Each PAL block in the M4-96/96 (Figure 7) contains a clock generator, a 98-product-term logic
array, a logic allocator, 16 macrocells, an output switch matrix, 16 I/O cells, and an input switch
matrix. The central switch matrix feeds each PAL block with 33 inputs. This makes the PAL block
look effectively like an independent “PALCE33V16”.
In addition to the logic product terms, individual output enable product terms and two PAL block
initialization product term are provided. Each I/O pin can be individually enabled. All flip-flops
that are in the synchronous mode within a PAL block are initialized together by either of the PAL
block initialization product terms.
The Central Switch Matrix and Input Switch Matrix
The M4-96/96 central switch matrix is fed by the input switch matrices in each PAL block. Each
PAL block provides 16 internal feedback signals and 16 I/O pin signals to the input switch matrix.
Of these 32 signals, 24 decoded signals are provided to the central switch matrix by the input
switch matrix. The central switch matrix distributes these signals back to the PAL blocks in a very
efficient manner that provides for high performance. The design software automatically configures
the input and central switch matrices when fitting a design into the device. The input switch matrix
(Figure 2) optimizes routing of inputs to the central switch matrix. Without the input switch matrix,
each input and feedback signal has only one way to enter the central switch matrix. The input
switch matrix provides additional ways for these signals to enter the central switch matrix.
Clock/Input
Dedicated
Input Pins
Pins
Figure 1. MACH4-96/96 Block Diagram and PAL Block Structure
33
Generator
Switch
Matrix
Clock
Logic
Array
Input
with XOR
Allocator
MACH4-96/96-15
Logic
16
4
16
PAL Block
PAL Block
Macrocells
Output
PAL Block
16
16
16
21535A-1
Pins
Pins
Pins
I/O
I/O
I/O
V A N T I S
7