MC56F8347 Freescale Semiconductor, Inc, MC56F8347 Datasheet - Page 10
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MC56F8347
Manufacturer Part Number
MC56F8347
Description
56f8300 16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC56F8347.pdf
(172 pages)
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1.4 Architecture Block Diagram
Note: Features in italics are NOT available in the 56F8147 device and are shaded in the following figures.
The 56F8347/56F8147 architecture is shown in
Figure 1-1
and
Figure
1-2.
Figure 1-1
illustrates how the
56800E system buses communicate with internal memories, the external memory interface and the IPBus
Bridge.
Table 1-2
lists the internal buses in the 56800E architecture and provides a brief description of
their function.
Figure 1-2
shows the peripherals and control blocks connected to the IPBus Bridge. The
figures do not show the on-board regulator and power and ground signals. They also do not show the
multiplexing between peripherals or the dedicated GPIOs. Please see
Part 2, Signal/Connection
Descriptions,
to see which signals are multiplexed with those of other peripherals.
Also shown in
Figure 1-2
are connections between the PWM, Timer C and ADC blocks. These
connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The
Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its conversions.
In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer
C input channel as indicated. The timer can then be used to introduce a controllable delay before
generating its output signal. The timer output then triggers the ADC. To fully understand this interaction,
please see the 56F8300 Peripheral User’s Manual for clarification on the operation of all three of these
peripherals.
56F8347 Technical Data, Rev.11
10
Freescale Semiconductor
Preliminary
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