MC56F8347 Freescale Semiconductor, Inc, MC56F8347 Datasheet - Page 119

• Manufacturer Part Number: MC56F8347
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as
the main processor frequency in this architecture. The maximum frequency of operation is
SYS_CLK = 60MHz.
6.8 Stop and Wait Mode Disable Function
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest
power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering
Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E
system clock must be set equal to the oscillator output.
Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those
instructions, write to the SIM control register (SIM_CONTROL), described in
can be on either a permanent or temporary basis. Permanently assigned applications last only until their
next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin and
the Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within
the SIM itself by writing to the SIM_CONTROL register and the COP reset.
Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is sequenced
to permit proper operation of the device. A POR reset is first extended for 2
stabilization of the clock source, followed by a 32 clock window in which SIM clocking is initiated. It is
then followed by a 32 clock window in which peripherals are released to implement Flash security, and,
Freescale Semiconductor
Preliminary
Permanent
Disable
Clock
Select
Reprogrammable
Disable
Figure 6-16 Internal Stop Disable Circuit
Reset
56F8347 Technical Data, Rev.11
D
D
D-FLOP
C
D
D-FLOP
C
R
Q
Q
Note: Wait disable circuit is similar
STOP_DIS
56800E
Stop and Wait Mode Disable Function
Part
21
clock cycles to permit
6.5.1. This procedure
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