MC56F8366 Freescale Semiconductor, Inc, MC56F8366 Datasheet - Page 84

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MC56F8366

Manufacturer Part Number
MC56F8366
Description
56f8300 16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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5.3.3
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes
fast interrupts before the core does.
A fast interrupt is defined (to the ITCN) by:
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its fast interrupt handling.
84
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt
Fast Interrupt Handling
1. See IPIC field definition in
IPIC_LEVEL[1:0]
00
01
10
11
Table 5-2 Interrupt Priority Encoding
1
No Interrupt or SWILP
Priority 0
Priority 1
Priorities 2 or 3
56F8366 Technical Data, Rev. 6
Part
Current Interrupt
Priority Level
5.6.30.2.
Priority 3
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Exception Priority
Required Nested
Freescale Semiconductor
Preliminary

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