LMX2310U National Semiconductor Corporation, LMX2310U Datasheet - Page 22

• Manufacturer Part Number: LMX2310U
• Description: Pllatinum? Ultra Low Power Frequency Synthesizer For Rf Personal Communicationscommunications
• Manufacturer: National Semiconductor Corporation

www.national.com
1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe-
sizer such as the National Semiconductor LMX2310/1/2/3U,
a voltage controlled oscillator (VCO), and a passive loop
filter. The frequency synthesizer includes a phase detector, a
current mode charge pump, as well as a programmable
reference divider and feedback frequency divider. The VCO
frequency is established by dividing the crystal reference
signal down via the reference divider to obtain a frequency
that sets the comparison frequency. This reference signal, f
is then presented to the input of a phase/frequency detector
and compared with another signal, f
1.1 REFERENCE OSCILLATOR
The reference oscillator frequency for the RF PLL is provided
from the external source via the OSC
reference buffer circuit supports frequencies from 2 MHz to
50 MHz with a minimum input sensitivity of 0.5 V
can be driven from an external CMOS or TTL logic gate. The
output of this buffer drives the R COUNTER. The output of
the buffer also connects to an oscillator/buffer circuit. Its
output connects to the OSC
cuit can be used as a buffer to provide the reference fre-
quency to other circuitry. It can also be used as an oscillator
with a crystal/resonator with proper components connected
between OSC
frequency.
1.2 REFERENCE DIVIDER (R COUNTER)
The reference divider is comprised of a 15-bit CMOS binary
counter that supports a continuous integer divide range from
2 to 32,767. The divide ratio should be chosen such that the
maximum phase comparison frequency of 10 MHz is not
exceeded. The reference divider circuit is clocked by the
output of the reference buffer circuit. The output of the
reference divider circuit feeds the reference input of the
phase detector circuit. The frequency of the reference input
to the phase detector (also referred to as the comparison
frequency) is equal to reference oscillator frequency divided
by the reference divider ratio. Refer to Section 3.2.1 for
details on programming the R COUNTER.
1.3 PRESCALERS
The LMX2310/1/2U contains a selectable, dual modulus
32/33 and 16/17 prescaler. The LMX2313U contains a se-
lectable, dual modulus 16/17 and 8/9 prescaler.
F
IN
Frequency
>
Input
PLL
1.2 GHz
in
and OSC
LMX2310/1U
out
Numbers
out
PLL
Part
pins to generate a reference
pin. The oscillator/buffer cir-
p
, which was obtained by
in
pin. The low noise
Allowable
32/33
Prescaler
pp
Values
. The input
r
,
22
dividing the VCO frequency down by way of the feedback
counter. The phase/frequency detector measures the phase
error between the f
nals that are directly proportional to the phase error. The
charge pump then pumps charge into or out of the loop filter
based on the magnitude and direction of the phase error.
The loop filter converts the charge into a stable control
voltage for the VCO. The phase/frequency detector’s func-
tion is to adjust the voltage presented to the VCO until the
feedback signal’s frequency and phase match that of the
reference signal. When this “phase-locked” condition exists,
the RF VCO frequency will be N times that of the comparison
frequency, where N is the feedback divider ratio.
The complimentary F
a bipolar, differential-pair amplifier. The output of the bipolar,
differential-pair amplifier drives a chain of ECL D-type flip-
flops in a dual modulus configuration. The output of the
prescaler is used to clock the subsequent programmable
feedback divider. Refer to Section 3.3.2 for details on pro-
gramming the Prescaler Value.
1.4 FEEDBACK DIVIDER (N COUNTER)
The N COUNTER is clocked by the output of the prescaler.
The N COUNTER is composed of a 13-bit programmable
integer divider. The 5-bit swallow counter is part of the
prescaler. Selecting a 32/33 prescaler provides a minimum
continuous divider range from 992 to 262,143 while selecting
a 16/17 prescaler value allows for continuous divider values
from 240 to 131,071. In the LMX2313U, selecting a 8/9
prescaler provides a minimum continuous divider range from
56 to 65535.
N = (P x NB_CNTR) + NA_CNTR
F
F
F
P
NA_CNTR
NB_CNTR
IN
φ
IN
F
F
MHz
IN
IN
Frequency
= N x F
≤ 1.2 GHz
≤ 600
Input
PLL
φ
Definitions
Phase Detector Comparison Frequency
RF Input Frequency
Prescaler Value
A Counter Value
B Counter Value
r
and f
IN
and F
LMX2310/1/2U
LMX2313U
p
Numbers
signals and outputs control sig-
INB
Part
PLL
20043829
input pins drive the input of
Allowable
16/17 or
32/33
8/9 or
16/17
Prescaler
Values