LMX2310U National Semiconductor Corporation, LMX2310U Datasheet - Page 27

• Manufacturer Part Number: LMX2310U
• Description: Pllatinum? Ultra Low Power Frequency Synthesizer For Rf Personal Communicationscommunications
• Manufacturer: National Semiconductor Corporation

Register
3.0 Programming Description
3.2.5 FoLD2,1,0
The FoLD2, FoLD1 and FoLD0 are used to select which signal is routed to FoLD pin.
3.3 N REGISTER
The N register contains the PWDN (Power-Down), P (Prescaler), NA_CNTR, and NB_CNTR control words. The detailed
descriptions and programming information for each control word is discussed in the following sections.
3.3.1 PWDN
The PWDN control bit along with CP
or asynchronous powered down by first setting the CP
Power-Down mode, the CP
3.3.2 P
The LMX2310/1/2/3U contains two dual modulus prescalers. The P control bit is used to set the prescaler value.
N
FoLD2
T[14]
0
0
0
0
1
1
1
1
PWDN
21
Prescaler
Most Significant Bit
Power-Down
20
P
FoLD Output Truth Table
FoLD1
19
R[21]
N[20]
0
0
1
1
0
0
1
1
o
_TRI bit will have to be reset to 0.
N[20]
18
0
1
PWDN
N[21]
0
1
1
N[21]
o
17
PLL Input Frequency
_TRI control bit is used to power-down the PLL. The LMX2310/1/2/3U can be synchronous
F
F
F
IN
IN
16
IN
≤ 600 MHz
>
CP
≤ 1.2 GHz
FoLD0
R[20]
R[19]
1.2 GHz
15
O
0
1
0
1
0
1
0
1
0
0
1
_TRI
B_CNTR[12:0]
SHIFT REGISTER BIT LOCATION
(Continued)
T[14],R[21],R[20]
14
o
_TRI bit and then setting the PWDN bit. To power up from the synchronous
Prescaler Value
LMX2310/1/2U
Data Field
13
16/17
32/33
Power-down (Asynchronous)
Disabled (TRI-STATE FoLD)
Lock Detect — Analog (Push/Pull), Reference to V
Lock Detect — Analog (Open Drain)
Reset R and N Dividers and TRI-STATE Charge Pump
Lock Detect — Digital (Push/Pull), Reference to V
R COUNTER Output (Push/Pull), Reference to V
N Counter Output (Push/Pull), Reference to V
Reserved (Do Not Use)
27
Power-down (Synchronous)
12
Allowable Prescaler Values
Normal Operation
Operating Mode
11
16/17 or 32/33
8/9 or 16/17
10
32/33
9
FoLD Output State
8
Prescaler Value
7
LMX2313U
16/17
8/9
6
A_CNTR[4:0]
5
4
Least Significant Bit
3
µC
µC
µC
µc
2
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Address
1
0
Field
0
1