LMX2310U National Semiconductor Corporation, LMX2310U Datasheet - Page 23

• Manufacturer Part Number: LMX2310U
• Description: Pllatinum? Ultra Low Power Frequency Synthesizer For Rf Personal Communicationscommunications
• Manufacturer: National Semiconductor Corporation

1.0 Functional Description
1.5 PHASE/FREQUENCY DETECTORS
The phase/frequency detector is driven from the N and R
COUNTER outputs. The maximum frequency at the phase
detector inputs is 10 MHz. The phase detector outputs con-
Note 13: The minimum width of the pump up and pump down current pulses occur at the CP
Note 14: The diagram assumes that PD_POL = 1
Note 15: f
Note 16: f
Note 17: CP
1.6 CHARGE PUMP
The charge pumps directs charge into or out of an external
loop filter. The loop filter converts the charge into a stable
control voltage which is applied to the tuning input of a VCO.
The charge pump steers the VCO control voltage towards V
during pump-up events and towards GND during pump-
down events. When locked, CP
condition with small corrections occurring at the phase com-
parison rate. The charge pump output current magnitude can
be selected as 1.0 mA or 4.0 mA by programming the
ICPo_4X bits. When TO_CNTR[11:0] = 1, the charge pump
output current magnitude is set to 4.0 mA. Refer to Section
3.2.3 and 3.4.2 for details on programming the charge pump
output current magnitude.
1.7 MICROWIRE SERIAL INTERFACE
The programmable register set is accessed through the
MICROWIRE serial interface. The interface is comprised of
three signal pins: CLOCK, DATA and LE (Latch Enable). The
MICROWIRE circuitry is referenced to V
circuitry to operate down to a 1.72V source. Serial data is
clocked into a 22-bit shift register from DATA on the rising
edge of CLOCK. The serial data is clocked in MSB first. The
last two bits decode the internal register address. On the
rising edge of LE, the data stored in the shift register is
loaded into one of the three latches based on the address
bits. The synthesizer can be programmed even in the power-
down state. A complete programming description is in Sec-
tion 3.0.
1.8 MULTI-FUNCTION OUTPUTS
The LMX2310/1/2/3U FoLD output pin is a multi-function
output that can be configured as an analog lock detect, a
digital lock detect, and a monitor of the output of the refer-
r
p
is the phase comparator input from the R Divider
is the phase comparator input from the N Divider
o
is charge pump output
Phase Comparator and Internal Charge Pump Characteristics
o
is primarily in a TRI-STATE
µC
, which allows the
(Continued)
P
23
trol the charge pump. The polarity of the pump-up or pump-
down control signals are programmed using the PD_POL
control bit, depending on whether the RF VCO tuning char-
acteristics are positive or negative (see programming de-
scription in Section 3.2.2). The phase/frequency detector
has a detection range of −2π to +2π.
ence divider and the feedback divider circuits. The FoLD
output pin is referenced to the V
FoLD1 and FoLD2 bits are used to select the desired output
function. A complete programming description of the FoLD
output pin is in Section 3.2.5.
1.8.1 Analog Lock Detect
When programmed for analog lock detect, the analog lock
detect status is available on the FoLD output pin. When the
charge pump is inactive, the lock detect output goes to a
high impedance in the open drain configuration and to a V
source in a push-pull configuration. It goes low when the
charge pump is active during a comparison cycle. The ana-
log lock detect status can be programmed in either an open
drain or push-pull configuration. The push-pull output is ref-
erenced to V
1.8.2 Digital Lock Detect
When programmed for digital lock detect, the digital lock
detect status is available on the FoLD pin. The digital lock
detect filter compares the phase difference of the inputs from
the phase detector to a RC generated delay of approxi-
mately 15 ns. To enter the locked state (LD = High), the
phase error must be less than the 15 ns RC delay for 5
consecutive reference cycles. Once in lock, the RC delay is
changed to approximately 30 ns. To exit the locked state, the
phase error must be greater than the 30 ns RC delay. When
a PLL is in power-down mode, the respective lock detect
output is always low. A flow chart of the digital lock detect
filter follows:
o
pin when the loop is phase-locked.
µC
.
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