LMX2310U National Semiconductor Corporation, LMX2310U Datasheet - Page 28

• Manufacturer Part Number: LMX2310U
• Description: Pllatinum? Ultra Low Power Frequency Synthesizer For Rf Personal Communicationscommunications
• Manufacturer: National Semiconductor Corporation

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Register
Count
FL Pin Forced TRI-STATE
FL Pin Forced Low
FL Pin Forced Low
FL Pin Forced High
Min Count (4)
Max Count (4095)
•
3.0 Programming Description
3.3.3 B_CNTR[12:0]
The NB_CNTR control word is used to program the B counter. The B counter is a 13-bit binary counter used in the programmable
feedback divider. The B counter can be programmed to values ranging from 3 to 8,191. See Section 1.4 for details on how the
value of the B counter should be selected.
NOTE: B counter divide ratio must be ≥ 3.
3.3.4 A_CNTR[4:0]
The NA_CNTR control word is used to program the A counter. The A counter is a 5-bit swallow counter used in the programmable
feedback divider. The A counter can be programmed to values ranging from 0 to 31. See Section 1.4 for details on how the value
of the A counter should be selected.
3.4 T REGISTER
The T register contains the TO_CNTR control word and FoLD2 control bit. The detailed descriptions and programming
information for each control word is discussed in the following sections.
3.4.1 FoLD2
See Section 3.2.5 for FoLD Output Truth Table details.
3.4.2 TO_CNTR[11:0]
When the Fastlock Timeout counter (TO_CNTR) is loaded with 0, Fastlock is off, the FL pin will be in TRI-STATE mode, and the
charge pump current will be the value specified by the Charge Pump Magnitude bit, R[18]. When the Timeout counter is loaded
with 1, the FL pin is 0 (pulled low) and the charge pump current will be at the 4X state. When the Timeout counter is loaded with
2, the FL pin will again be set to 0 (pulled low), but the charge pump current will be controlled by R[18]. When the Timeout counter
is loaded with 3, the FL pin is 1 (pulled high) with the charge pump current will be controlled by R[18]. When loaded with 4 through
4095, Fastlock is active and will time-out after the specified number of phase detector events.
Divider Value
T
8,191
3
4
•
21
0
Most Significant Bit
20
0
FoLD Output (P/O Output Truth Table)
19
0
0
0
1
•
NOTES: A counter divide ratio must be ≤ P and A counter divide ratio must be ≤ B counter divide ratio.
A Counter
B COUNTER
Divide
18
Timeout Counter Table
Ratio
0
TO_CNTR[11:0]
0
0
0
0
0
1
•
31
0
1
•
0
0
1
•
17
0
0
0
0
0
1
0
•
0
0
0
0
0
1
•
16
0
N[6:2]
0
0
1
•
0
0
0
0
0
1
•
0
0
1
•
N[19:7]
15
0
0
0
0
0
0
1
•
0
0
1
•
FoLD2
0
0
0
0
0
1
SHIFT REGISTER BIT LOCATION
•
14
(Continued)
0
0
0
0
0
1
T[13:2]
•
0
0
1
•
0
0
1
•
Data Field
13
0
0
0
0
0
1
•
T[14]
28
A_CNTR[4:0]
0
0
0
0
0
1
•
0
0
1
12
•
B_CNTR[12:0]
0
0
0
0
1
1
•
0
0
1
•
11
0
0
1
0
0
1
1
0
1
•
•
10
0
1
0
1
0
1
•
TO_CNTR[11:0]
Notes
C
C
C
C
C
when count reaches 0
0
0
1
9
•
0
0
1
•
P
P
P
P
P
current controlled by R[18]
= 4 mA (manual Fastlock mode)
current controlled by R[18]
current controlled by R[18]
Current set to 4 mA, switches to 1 mA
8
0
0
1
•
7
6
0
1
1
•
0
0
1
•
5
4
Least Significant Bit
0
1
1
•
3
2
1
0
1
•
Address
1
1
Field
0
1
1
1
•
0