HT45R35V Holtek Semiconductor Inc., HT45R35V Datasheet - Page 15

• Manufacturer Part Number: HT45R35V
• Description: C/r To F Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

The WDT overflow under normal operation will generate
a chip reset and set the status bit TO . But in the
Power Down mode, the overflow will generate a warm
reset , where only the Program Counter and Stack
Pointer are reset to zero. To clear the contents of the
WDT, including the WDT prescaler, three methods can
be used; an external reset (a low level to RES), a soft-
ware instruction and a HALT instruction. The software
instruction includes CLR WDT instruction and the in-
struction pair
these two types of instruction, only one can be active de-
pending on the configuration option
selection option . If the CLR WDT is selected, i.e.
CLRWDT times equal one, any execution of the CLR
WDT instruction will clear the WDT. In the case that
CLRWDT times equal two, these two instructions must
be executed to clear the WDT; otherwise, the WDT may
reset the chip as a result of a time-out.
Power Down Operation
The Power Down mode is initialized by the HALT in-
struction and results in the following...
The system can leave the Power Down mode by means
of an external reset, an interrupt, an external falling
edge signal on port Aor a WDT overflow. An external re-
Rev. 1.00
CLR WDT1 and CLR WDT2 are chosen, i.e.
The system oscillator will be turned off but the WDT
oscillator keeps running, if the internal WDT oscillator
has been selected as the WDT source clock.
The contents of the on chip RAM and registers remain
unchanged.
The WDT and WDT prescaler will be cleared and will
resume counting, if the internal WDT oscillator has
been selected as the WDT source clock
AlloftheI/Oportswillmaintaintheiroriginalstatus.
The PDF flag is set and the TO flag is cleared.
CLR WDT1 and CLR WDT2 . Of
CLR WDT times
15
set causes a device initialisation and the WDT overflow
performs a warm reset . After the TO and PDF flags
are examined, the reason for the device reset can be de-
termined. The PDF flag is cleared by a system power-up
or executing the CLR WDT instruction and is set when
a HALT instruction is executed. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer; the other
registers maintain their their original status.
The port A and interrupt methods of wake-up can be
considered as a continuation of normal execution. Each
bit in port A can be independently selected by configura-
tion options to wake-up the device. When awakened
from an I/O port stimulus, the program will resume exe-
cution at the next instruction. If it is awakened due to an
interrupt, two sequences may happen. If the related in-
terrupt is disabled or the interrupt is enabled but the
stack is full, the program will resume execution at the
next instruction. If the interrupt is enabled and the stack
is not full, the regular interrupt response takes place. If
an interrupt request flag is set to 1 before entering the
Power Down Mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 t
mal operation. A dummy period is therefore inserted af-
ter wake-up. If the wake-up results from an interrupt
acknowledgment, the actual interrupt subroutine execu-
tion will be delayed by one or more cycles. If the
wake-up results in the next instruction execution, this
will be executed immediately after the dummy period is
finished.
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power Down
mode.
SYS
(system clock periods) to resume nor-
January 15, 2009
HT45R35V