DSPIC33FJ64MC508 Microchip Technology Inc., DSPIC33FJ64MC508 Datasheet - Page 161

• Manufacturer Part Number: DSPIC33FJ64MC508
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

14.0
14.1
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single
output pulse.
To generate a single output pulse, the following steps
are required (these steps assume the timer source is
initially turned off, but this is not a requirement for the
module operation):
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. To initiate another single pulse output, change the
© 2007 Microchip Technology Inc.
Note:
Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
Calculate the time to the falling edge of the pulse,
based on the desired pulse width and the time to
the rising edge of the pulse.
Write the values computed in steps 2 and 3 above
into the Output Compare register, OCxR, and the
Output Compare Secondary register, OCxRS,
respectively.
Set the Timer Period register, PRy, to a value
equal to or greater than the value in OCxRS, the
Output Compare Secondary register.
Set the OCM bits to ‘100’ and the OCTSEL
(OCxCON<3>) bit to the desired timer source. The
OCx pin state will now be driven low.
Set the TON (TyCON<15>) bit to ‘1’, which
enables the compare time base to count.
Upon the first match between TMRy and OCxR,
the OCx pin will be driven high.
When the incrementing timer, TMRy, matches the
Output Compare Secondary register, OCxRS, the
second and trailing edge (high-to-low) of the pulse
is driven onto the OCx pin. No additional pulses
are driven onto the OCx pin and it remains at low.
As a result of the second compare match event,
the OCxIF interrupt flag bit is set, which will result
in an interrupt if the interrupt enable bit, OCxIE, is
set. For further information on peripheral
interrupts, refer to Section 6.0 “Interrupt Con-
troller”.
Timer and Compare register settings, if needed,
OUTPUT COMPARE
Setup for Single Output Pulse
Generation
This data sheet summarizes the features
of this group of dsPIC33FJXXXMCX06/
X08/X10 Motor Control Family devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F Family Reference Manual”.
Refer
(www.microchip.com)
dsPIC33F
chapters.
dsPIC33FJXXXMCX06/X08/X10 MOTOR CONTROL FAMILY
to
the
family
Microchip
reference
for
the
web
manual
latest
site
The output compare module does not have to be dis-
abled after the falling edge of the output pulse. Another
pulse can be initiated by rewriting the value of the
OCxCON register.
14.2
When the OCM control bits (OCxCON<2:0>) are set to
‘101’, the selected output compare channel initializes
the OCx pin to the low state and generates output
pulses on each and every compare match event.
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required (these steps assume the timer
source is initially turned off, but this is not a requirement
for the module operation):
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. As a result of the second compare match event,
11. When the compare time base and the value in its
12. Steps 8 through 11 are repeated and a continuous
and then issue a write to set the OCM bits to ‘100’.
Disabling and re-enabling the timer, and clearing
the TMRy register, are not required but may be
advantageous for defining a pulse from a known
event time boundary.
Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
Calculate the time to the falling edge of the pulse,
based on the desired pulse width and the time to
the rising edge of the pulse.
Write the values computed in step 2 and 3 above
into the Output Compare register, OCxR, and the
Output Compare Secondary register, OCxRS,
respectively.
Set the Timer Period register, PRy, to a value
equal to or greater than the value in OCxRS, the
Output Compare Secondary register.
Set the OCM bits to ‘101’ and the OCTSEL bit to
the desired timer source. The OCx pin state will
now be driven low.
Enable the compare time base by setting the TON
(TyCON<15>) bit to ‘1’.
Upon the first match between TMRy and OCxR,
the OCx pin will be driven high.
When the compare time base, TMRy, matches
the Output Compare Secondary register, OCxRS,
the second and trailing edge (high-to-low) of the
pulse is driven onto the OCx pin.
the OCxIF interrupt flag bit is set.
respective Timer Period register match, the TMRy
register resets to 0x0000 and resumes counting.
stream of pulses is generated, indefinitely. The
OCxIF flag is set on each OCxRS-TMRy compare
match event.
Setup for Continuous Output
Pulse Generation
DS70287A-page 159