DSPIC33FJ64MC508 Microchip Technology Inc., DSPIC33FJ64MC508 Datasheet - Page 193

• Manufacturer Part Number: DSPIC33FJ64MC508
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 16-2:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-9
bit 8
bit 7
bit 6-4
bit 3-0
QEOUT
R/W-0
U-0
—
Unimplemented: Read as ‘0’
IMV<1:0>: Index Match Value bits – These bits allow the user to specify the state of the QEA and QEB
In 4X Quadrature Count Mode:
In 2X Quadrature Count Mode:
CEID: Count Error Interrupt Disable bit
1 = Interrupts due to count errors are disabled
0 = Interrupts due to count errors are enabled
QEOUT: QEA/QEB/INDX Pin Digital Filter Output Enable bit
1 = Digital filter outputs enabled
0 = Digital filter outputs disabled (normal pin operation)
QECK<2:0>: QEA/QEB/INDX Digital Filter Clock Divide Select Bits
111 = 1:256 Clock Divide
110 = 1:128 Clock Divide
101 = 1:64 Clock Divide
100 = 1:32 Clock Divide
011 = 1:16 Clock Divide
010 = 1:4 Clock Divide
001 = 1:2 Clock Divide
000 = 1:1 Clock Divide
Unimplemented: Read as ‘0’
dsPIC33FJXXXMCX06/X08/X10 MOTOR CONTROL FAMILY
input pins during an index pulse when the POSCNT register is to be reset.
IMV1= Required state of Phase B input signal for match on index pulse
IMV0= Required state of Phase A input signal for match on index pulse
IMV1= Selects phase input signal for index state match (0 = Phase A, 1 = Phase B)
IMV0= Required state of the selected Phase input signal for match on index pulse
U-0
—
DFLTCON: DIGITAL FILTER CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
QECK<2:0>
R/W-0
U-0
—
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
R/W-0
U-0
—
IMV<2:0>
x = Bit is unknown
R/W-0
U-0
—
DS70287A-page 191
R/W-0
CEID
U-0
—
bit 8
bit 0