PDU18F Data Delay Devices, Inc., PDU18F Datasheet

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PDU18F

Manufacturer Part Number
PDU18F
Description
8-bit Programmable Delay Line
Manufacturer
Data Delay Devices, Inc.
Datasheet
1.PDU18F.pdf (5 pages)
8-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU18F)
FEATURES
•
•
•
•
•
•
•
•
FUNCTIONAL DESCRIPTION
The PDU18F-series device is a 8-bit digitally programmable delay line.
The delay, TD
depends on the address code (A7-A0) according to the following formula:
where A is the address code, T
and TD
specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced into
LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal
operation.
SERIES SPECIFICATIONS
•
•
•
•
•
•
•
•
Doc #97006
1/30/06
Digitally programmable in 256 delay steps
Monotonic delay-versus-address variation
Two separate outputs: inverting & non-inverting
Precise and stable delays
Input & outputs fully TTL interfaced & buffered
10 T
Fits standard 40-pin DIP socket
Auto-insertable
Programmed delay tolerance: 5% or 2ns,
Inherent delay (TD
Setup time and propagation delay:
Operating temperature: 0° to 70° C
Temperature coefficient: 100PPM/°C (excludes TD
Supply voltage V
Supply current:
Minimum pulse width: 6% of total delay
0
TD
Address to input setup (T
Disable to output delay (T
2
is the inherent delay of the device. The incremental delay is
L fan-out capability
A
= TD
A
, from the input pin (IN) to the output pins (OUT, OUT/)
0
+ T
CC
I
I
0
CCH
CCL
INC
: 5VDC ± 5%
): 13ns typical (OUT)
* A
12ns typical (OUT/)
= 128ma
= 65ma
INC
whichever is greater
3 Mt. Prospect Ave. Clifton, NJ 07013
is the incremental delay of the device,
AIS
DISO
DATA DELAY DEVICES, INC.
):
): 6ns typ. (OUT)
10ns
OUT/
GND
GND
GND
GND
OUT
0
N/C
EN/
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
EN/
N/C
)
A7
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PDU18F-.5
PDU18F-1
PDU18F-2
PDU18F-3
PDU18F-4
PDU18F-5
PDU18F-6
PDU18F-8
PDU18F-10
NOTE: Any dash number between .5 and 10 not
DASH NUMBER SPECIFICATIONS
Number
Part
shown is also available.
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PACKAGES
VCC
N/C
A0
A1
A2
VCC
N/C
A3
A4
A5
VCC
N/C
N/C
N/C
N/C
VCC
N/C
A6
N/C
N/C
data
delay
devices,
Per Step (ns)
Incremental
PIN DESCRIPTIONS
IN
OUT Non-inverted Output
OUT/ Inverted Output
A0-A7 Address Bits
EN/
VCC +5 Volts
GND Ground
10 ± 2.0
3 ± 1.0
4 ± 1.0
5 ± 1.5
6 ± 1.5
8 ± 2.0
.5 ± .3
Delay
1 ± .5
2 ± .5
1997 Data Delay Devices
PDU18F-xx
PDU18F-xxC5
PDU18F-xxM
PDU18F-xxMC5
Delay Line Input
Output Enable
DIP
Gull-Wing
Military DIP
Military Gull-Wing
2,040 ± 102.0
2,550 ± 127.5
Change (ns)
1,020 ± 51.0
1,275 ± 63.8
1,530 ± 76.5
Total Delay
PDU18F
127.5 ± 6.4
255 ± 12.8
510 ± 25.5
765 ± 38.3
3
inc.
1

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PDU18F Summary of contents

Page 1

... L fan-out capability • Fits standard 40-pin DIP socket • Auto-insertable FUNCTIONAL DESCRIPTION The PDU18F-series device is a 8-bit digitally programmable delay line. The delay from the input pin (IN) to the output pins (OUT, OUT/) A depends on the address code (A7-A0) according to the following formula: TD ...

Page 2

... PDU18F ADDRESS UPDATE The PDU18F is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1. After the last signal edge to be delayed has appeared on the OUT pin, a minimum time required before the address lines can change ...

Page 3

... OH V 0. 0.1 IHH -0 -60 -150 OS 25 12.5 DATA DELAY DEVICES, INC. PDU18F TYP UNITS 255 T INC 14.0 ns 1 UNITS NOTES sec UNITS NOTES ...

Page 4

... DIP (PDU18F-xx, PDU18F-xxM) .020 TYP .090 Gull-Wing (PDU18F-xxC5, PDU18F-xxMC5) Doc #97006 1/30/06 Tel: 973-773-2299 PACKAGE DIMENSIONS .100 TYP. ...

Page 5

... Mt. Prospect Ave. Clifton, NJ 07013 TEST CONDITIONS OUTPUT Load load Threshold: PRINTER COMPUTER SYSTEM REF OUT IN TEST (DUT) TRIG Test Setup PER IN T FALL 2.4V 1. 1.5V 1.5V DATA DELAY DEVICES, INC. PDU18F 1 FAST-TTL Gate 5pf ± 10% 1.5V (Rising & Falling) TIME INTERVAL COUNTER ...

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