FIDO1100 Innovasic Semiconductor Inc., FIDO1100 Datasheet - Page 5

• Manufacturer Part Number: FIDO1100
• Description: 32-bit Real-time Communications Controller
• Manufacturer: Innovasic Semiconductor Inc.

Flexible Input Deterministic Output (fido
32-Bit Real-Time Communications Controller
Figure 1. Block Diagram for the fido1100......................................................................................8
Figure 2. PQFP Package Diagram ................................................................................................17
Figure 3. PQFP Physical Package Dimensions.............................................................................24
Figure 4. BGA 10- by 10-mm Package Diagram .........................................................................26
Figure 5. BGA 10- by 10-mm Physical Package Dimensions ......................................................33
Figure 6. BGA 15- by 15-mm Package Diagram .........................................................................35
Figure 7. BGA 15- by 15-mm Physical Package Dimensions ......................................................42
Figure 8. BGA 15- by 15-mm Signal Routing ..............................................................................44
Figure 9. Thermal Performance of PQFP/BGA Under Forced Convection .................................50
Figure 10. Reset Timing ...............................................................................................................53
Figure 11. Extended Reset Timing ...............................................................................................53
Figure 12. Driven Clock Source ...................................................................................................55
Figure 13. Crystal Oscillator Third Overtone Off-Chip Components .........................................55
Figure 14. Crystal Oscillator Fundamental Overtone Off-Chip Components ..............................55
Figure 15. Propagation Delay .......................................................................................................59
Figure 16. Setup Time...................................................................................................................59
Figure 17. Hold Time ....................................................................................................................60
Figure 18. Recovery Time ............................................................................................................60
Figure 19. Removal Time .............................................................................................................60
Figure 20. Minimum Pulse Width ................................................................................................61
Figure 21. External Bus Timing for a Single, 32-Bit Cycle (without RDY_N) ...........................62
Figure 22. External Bus Timing for a 32-Bit Transfer (with RDY_N) ........................................63
Figure 23. External Bus Timing for 8-Bit/16-Bit Transfer (without RDY_N).............................64
Figure 24. External Bus Timing for 8-Bit/16-Bit Transfer (with RDY_N) ..................................65
Figure 25. SDRAM CAS Timing .................................................................................................67
Figure 25. Specific Row Activation Timing .................................................................................68
Figure 27. Meeting tRCD (min) When 2 < tRCD (min)/tCK ≤ 3 ................................................68
Figure 28. SDRAM Read Operation Timing ................................................................................69
Figure 29. SDRAM Read Burst Timing .......................................................................................70
Figure 30. SDRAM Write Operation Timing ...............................................................................71
Figure 31. SDRAM Write Burst Timing ......................................................................................72
Figure 32. SDRAM Write-to-Write Timing .................................................................................72
Figure 33. SDRAM Write-to-Precharge Timing ..........................................................................73
Figure 34. JTAG State Machine ...................................................................................................74
Figure 35. JTAG Port Register Interface ......................................................................................75
Figure 36. Timing of JTAG Signals .............................................................................................75
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LIST OF FIGURES
UNCONTROLLED WHEN PRINTED OR COPIED
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IA211080807-07
Page 5 of 83
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Customer Support:
April 15, 2010
Data Sheet
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