FIDO1100 Innovasic Semiconductor Inc., FIDO1100 Datasheet - Page 66

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FIDO1100

Manufacturer Part Number
FIDO1100
Description
32-bit Real-time Communications Controller
Manufacturer
Innovasic Semiconductor Inc.
Datasheet

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Flexible Input Deterministic Output (fido ® )
32-Bit Real-Time Communications Controller
9.2
9.2.1 SDRAM CAS Timing
The CAS latency is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be set to two or three clocks. If
a READ command is registered at clock edge n, and the latency is m clocks, the data will be
available by clock edge n + m. The DQs will start driving because of the clock edge one cycle
earlier (n + m – 1) and, provided the relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming the clock cycle time is such that all relevant access
times are met, if a READ command is registered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in
Figure 24.
Note: This timing picture also reflects the default bus timing for all memory
addresses not decoded by the internal chip-select unit. In this case, the
timing is controlled by the External Bus Default Timing Register.
In the case of a write transfer, once the low active RDY_N line is first sampled low
(labeled with an arrow marked ―2‖ in the diagram), the write cycle will complete on the
next rising edge of the clock as shown (labeled with an arrow marked ―3‖ in the
diagram).
In the case of a read transfer, once the low active RDY_N line is first sampled low
(labeled with an arrow marked ―2‖ in the diagram), the read data will be sampled on the
second rising edge of the clock.
If the RDY_N line never goes low, the cycle will end (as a bus error) after a timeout of
TxWAIT + 256 clocks.
If the RDY_N line is unused (tied low via an internal pull down) or goes low
immediately, the cycle will be controlled by TxWAIT as shown above.
In the case of a write transfer, the write enable signal (WE_N) goes active (low) 0–3
clocks after the CS_N goes low.
The write enable signal (WE_N) goes inactive (hi) 0–3 clocks (TWER) before the end of
the chip-select time.
SDRAM Timing
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IA211080807-07
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April 15, 2010
Data Sheet
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