FIDO1100 Innovasic Semiconductor Inc., FIDO1100 Datasheet - Page 52

• Manufacturer Part Number: FIDO1100
• Description: 32-bit Real-time Communications Controller
• Manufacturer: Innovasic Semiconductor Inc.

Flexible Input Deterministic Output (fido ® )
32-Bit Real-Time Communications Controller
7.
7.1
This section describes the reset signal considerations and the reset timing. The Power On Reset
Register has a control bit to determine whether Major Reset or Minor Reset processing is
performed after reset is asserted. The section below presents the hardware signal characteristics.
See The fido1100 User Guide for more details on the Power On Reset Control Register.
7.2
The fido1100 requires the RESET_N signal to be asserted LOW for a minimum of 100 µS after
VDDIO and VDDC are at their nominal values and stable. The RESET_N signal must have a
rise time of less than 100 nS. Table 21 presents the hardware signals involved or affected and
should be considered when asserting reset.
Table 21. Hardware Signals Involved When Asserting Reset
When RESET_N is asserted, the following sequence occurs:
A_25_RESET_DELAY
RESET_OUT_N
Signal Name
A27_CS7_N
A28_CS6_N
A29_CS5_N
A30_CS4_N
A_26_SIZE
RESET_N
Note: After this delay, the part performs major or minor reset processing and is
released to run.
Reset
Overview
Signal Considerations and Reset Timing
The A25_Reset_Delay signal is sampled to determine the length of the reset clock delay
– Low—reset clock delay → 100 µsecs
– High—reset clock delay → 20 msecs
The A_26_SIZE pin is sampled for the external bus interface size
– Low—8-bit width
– High—16-bit width
CS0_N
®
Muxed, Internal
Muxed, Internal
Pull-up
Pull-up
Output
Muxed
Muxed
Muxed
Muxed
Output
Input
Type
UNCONTROLLED WHEN PRINTED OR COPIED
Reset input
Reset output
Muxed pin, External Bus Interface address Bit [25] or
POR counter bypass
Muxed pin, External Bus Interface address Bit [26] or data
bus size select (0 = 8-bit, 1 = 16-bit)
Muxed pin, External Bus Interface address Bit [27] or
Chip select 7 (chip select active low)
Muxed pin, External Bus Interface address Bit [28] or
Chip select 6 (chip select active low)
Muxed pin, External Bus Interface address Bit [29] or
Chip select 5 (chip select active low)
Muxed pin, External Bus Interface address Bit [30] or
Chip select 4 (chip select active low)
Chip select 0 (chip select active low)
Page 52 of 83
IA211080807-07
Description
http://www.Innovasic.com
Customer Support:
April 15, 2010
Data Sheet
1-888-824-4184