ST92185B STMicroelectronics, ST92185B Datasheet
ST92185B
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ST92185B Summary of contents
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... Real-Time Operating System available from third parties Pin-compatible EPROM and OTP devices available (ST92E195D7D1, ST92T195D7B1) Pin-compatible with the ST92195 family with embedded teletext decoder Device Summary Device ST92185B1 ST92185B2 ST92185B3 ST92185B PSDIP56 PSDIP42 TQFP64 development tools, including Linker, C-compiler, Archiver, Debugger ...
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... ST92185B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 ST9+ Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.3 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 TV Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.5 On Screen Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... ST9 core from I/O and data management processing tasks allowing criti- cal application tasks to get the maximum use of core resources. The ST92185B MCU supports low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 ST9+ Core ...
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... The SPI uses a single data line for data input and output. A second line is used for a syn- chronous clock signal. 1.1.9 Standard Timer (STIM) The ST92185B has one Standard Timer (STIM0) that includes a programmable 16-bit down counter and an associated 8-bit prescaler with Single and Continuous counting modes. ...
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... ST92185B - GENERAL DESCRIPTION INTRODUCTION (Cont’d) Figure 1. ST92185B Block Diagram 24/32 Kbytes ROM 256 bytes RAM 2 Kbytes TDSRAM TRI 256 bytes Register File 8/16-bit CPU MMU NMI INT[7:4] Interrupt INT2 Management INT0 ST9+ CORE OSCIN OSCOUT RCCU RESET RESETO 16-BIT TIMER/ WATCHDOG ...
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... OSCOUT is the output of the oscillator inverter. Figure 2. 56-Pin Package Pin-Out CSO/RESET0/P3.7 SCK/INT2/P5.0 ST92185B - GENERAL DESCRIPTION VSYNC Vertical Sync . Vertical video synchronisa- tion input to OSD. Positive or negative polarity. HSYNC/CSYNC Horizontal/Composite sync . Hori- zontal or composite video synchronisation input to OSD. Positive or negative polarity. ...
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... ST92185B - GENERAL DESCRIPTION PIN DESCRIPTION (Cont’d) Figure 3. ST92185B Required External components (56-pin package) 10/178 ...
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... PIN DESCRIPTION (Cont’d) Figure 4.. 42-Pin Package Pin-Out INT7/P2.0 AIN4/P0.2 CSO/RESET0/P3.7 SDI/SDO/P5.1 SCK/INT2/P5.0 ST92185B - GENERAL DESCRIPTION RESET ...
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... ST92185B - GENERAL DESCRIPTION Figure 5. ST92185B Required External Components (42-pin package) 12/178 ...
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... Figure 6. 64-Pin Package Pin-Out GND AIN4/P0.2 P0.1 P0.0 CSO/RESET0/P3.7 P3.6 P3.5 P3 SDO/SDI/P5.1 INT2/SCK/P5 JTDO Note: N.C = Not connected ST92185B - GENERAL DESCRIPTION P4.7/PWM7/EXTRG/STOUT P4.6/PWM6 P4.5/PWM5 P4.4/PWM4 P4.3/PWM3/TSLU/HT P4.2/PWM2 P4.1/PWM1 P4.0/PWM0 VSYNC HSYNC/CSYNC AVDD1 PXFM JTRST0 GND N.C. 32 13/178 ...
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... P4.1 29 P4.2 30 P4.3 31 P4.4 32 14/178 Important : Note that open-drain outputs are for logic levels only and are not true open drain. 1.2.1 I/O Port Alternate Functions. Each pin of the I/O ports of the ST92185B may as- sume software programmable Alternate Functions (see Table 1). Pin No. SDIP56 10 I/O 9 I/O 8 AIN4 I A/D Analog Data Input 4 ...
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... Port General Purpose I/O Name SDIP42 P4.5 33 P4.6 34 All ports useable for general pur- P4.7 35 pose I/O (input, output or bidi- rectional) P5.0 20 P5.1 19 ST92185B - GENERAL DESCRIPTION Pin No. SDIP56 47 PWM5 O PWM Output 5 48 PWM6 O PWM Output 6 EXTRG I A/D Converter External Trigger Input 49 PWM7 O PWM Output 7 STOUT O Standard Timer Output ...
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... ST92185B - GENERAL DESCRIPTION PIN DESCRIPTION (Cont’d) 1.2.2 I/O Port Styles Pins Weak Pull-Up P0[7:0] no P2[5,4,3,2] no P2[1,0] no P3.7 yes P3[6,5,4] no P4[7:0] no P5[1:0] no Legend: AF= Alternate Function, BID = Bidirectional Open Drain PP = Push-Pull, TTL = TTL Standard Input Levels How to Read this Table To configure the I/O ports, use the information in this table and the Port Bit Configuration Table in ...
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... The ROM memory is mapped in a single continu- ous area starting at address 0000h in MMU seg- ment 00h. Device Size Address ST92185B1 16K ST92185B2 24K ST92185B3 32K Figure 7. ST92185B Memory Map 2287FFh 2Kbytes TDSRAM 228000h 20FFFFh Internal RAM 256 bytes 20FF00h 007FFFh 32 Kbytes ...
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... ST92185B - GENERAL DESCRIPTION 1.4 REGISTER MAP The following pages contain a list of ST92185B registers, grouped by peripheral or function. Be very careful to correctly program both: – The set of registers dedicated to a particular function or peripheral. – Registers common to other functions. Group F Pages Register Map Register Page 0 2 R255 Res ...
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... R241 0 R242 R248 I/O 2 Port R249 2 R250 R252 I/O Port R253 3 R254 ST92185B - GENERAL DESCRIPTION Register Description Name P0DR Port 0 Data Register P2DR Port 2 Data Register P3DR Port 3 Data Register P4DR Port 4 Data Register P5DR Port 5 Data Register CICR Central Interrupt Control Register ...
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... ST92185B - GENERAL DESCRIPTION Group F Reg. Page Block No. Dec. R240 I/O Port R241 4 R242 3 I/O R244 Port R245 5 R246 R240 R241 11 STIM R242 R243 R240 R241 R242 MMU R243 21 R244 R248 R249 Ext.Mem. R246 R240 HBLANKR R241 R242 R243 R244 R245 R246 CHPOSR R247 ...
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... R255 R240 62 ADC R241 R242 Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register description for details. ST92185B - GENERAL DESCRIPTION Register Description Name PXCCR PLL Clock Control Register SLCCR Slicer Clock Control Register MCCR ...
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... ST92185B - DEVICE ARCHITECTURE 2 DEVICE ARCHITECTURE 2.1 CORE ARCHITECTURE The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats; 14 address- ing modes are available. Four independent buses are controlled by the ...
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... E SYSTEM REGISTERS 224 223 ST92185B - DEVICE ARCHITECTURE Figure 10. Page Pointer for Group F mapping PAGES R255 R240 R234 224 R224 GENERAL PURPOSE REGISTERS VA00432 R0 R195 (R0C3h) (1100) (0011 PAGE 63 PAGE 5 PAGE 0 ...
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... ST92185B - DEVICE ARCHITECTURE MEMORY SPACES (Cont’d) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus R231, RE7h and R11100111b represent the same register (see Figure 4) ...
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... CE bit in the TCR Register (only in devices featur- ing the MFT Multifunction Timer) in order to enable the Timers when both bits are set. This bit is set af- ter the Reset cycle. ST92185B - DEVICE ARCHITECTURE Table 2 System Note MFT is not included in the ST9 device, then this bit has no effect. ...
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... ST92185B - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt service rou- tine, thus returning the CPU to its original status. ...
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... Register File is to operate in single 16-register mode or in twin 8-register mode. The srp instruc- tion selects the single 16-register group mode and ST92185B - DEVICE ARCHITECTURE specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatical- ly select the twin 8-register group mode and spec- ify the locations of each 8-register block ...
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... ST92185B - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) 7 RG4 RG3 RG2 RG1 RG0 Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions ...
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... r15 ST92185B - DEVICE ARCHITECTURE Figure 13. Pointing to two groups of 8 registers BLOCK NUMBER REGISTER POINTER 0 set by: srp #2 instruction points to: addressed by BLOCK 7 GROUP 1 addressed by BLOCK 2 REGISTER GROUP REGISTER FILE 31 REGISTER F POINTER 0 30 & ...
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... ST92185B - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) 2.3.4 Paged Registers pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9 devices. ...
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... Bit 1 = BRQEN: Bus Request Enable . 0: External Memory Bus Request disabled 1: External Memory Bus Request enabled on BREQ pin (where available). ST92185B - DEVICE ARCHITECTURE Note: Disregard this bit if BREQ pin is not availa- ble. Bit 0 = HIMP: High Impedance Enable . When any of Ports depending on de- ...
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... ST92185B - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) state by setting the HIMP bit. When this bit is reset, it has no effect. Setting the HIMP bit is recommended for noise re- duction when only internal Memory is used. If Port 1 and/or 2 are declared as an address AND as an I/O port (for example: P10... P14 = Address, and P15 ...
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... FILE STACK POINTER (LOW STACK ST92185B - DEVICE ARCHITECTURE SYSTEM STACK POINTER HIGH REGISTER (SSPHR) R238 - Read/Write Register Group: E (System) Reset value: undefined 0 7 USP8 SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SYSTEM STACK POINTER LOW REGISTER (SSPLR) ...
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... ST92185B - DEVICE ARCHITECTURE 2.4 MEMORY ORGANIZATION Code and data are accessed within the same line- ar address space. All of the physically separate memory areas, including the internal ROM, inter- nal RAM and external memory are mapped in a common address space. The ST9 provides a total addressable memory space of 4 Mbytes. This address space is ar- ranged as 64 segments of 64 Kbytes ...
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... F1h R241 DPR0 F0h R240 ST92185B - DEVICE ARCHITECTURE sub-divided into 2 main groups: a first group of four 8-bit registers (DPR[3:0]), and a second group of three 6-bit registers (CSR, ISR, and DMASR). The first group is used to extend the address during Data Memory access (DPR[3:0]). The second is ...
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... ST92185B - DEVICE ARCHITECTURE 2.6 ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a 22-bit physical address. There are 2 different ways to do this de- pending on the memory involved and on the oper- ation being performed ...
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... DMA Fetching interrupt 3 instruction or DMA access to Program Memory ST92185B - DEVICE ARCHITECTURE Most of these registers do not have a default value after reset. 2.7.1 DPR[3:0]: Data Page Registers The DPR[3:0] registers allow access to the entire 4 Mbyte memory space composed of 256 pages of 16 Kbytes. 2.7.1.1 Data Page Register Relocation ...
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... ST92185B - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. 7 DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0 Bits 7:0 = DPR0_[7:0]: These bits define the 16- Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to ex- tend the address during a Data Memory access ...
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... Reset value: undefined ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0 ST92185B - DEVICE ARCHITECTURE ISR and ENCSR bit (EMR2 register) are also de- scribed in the chapter relating to Interrupts, please refer to this description for further details. Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = ISR_[5:0]: These bits define the 64- ...
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... ST92185B - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) Figure 19. Memory Addressing Scheme (example) DPR3 DPR2 DPR1 DPR0 DMASR ISR CSR 40/178 4M bytes 16K 16K 16K 64K 64K 16K 64K 3FFFFFh 294000h 240000h 23FFFFh 20C000h 200000h 1FFFFFh 040000h 03FFFFh 030000h 020000h 010000h 00C000h ...
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... If this bit is reset (default condition), the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, the ISR is ST92185B - DEVICE ARCHITECTURE used instead of the CSR, and the interrupt stack frame is kept exactly as in the original ST9 (only the PC and flags are pushed). This avoids the ...
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... ST92185B - INTERRUPTS 3 INTERRUPTS 3.1 INTRODUCTION The ST9 responds to peripheral and external events through its interrupt channels. Current pro- gram execution can be suspended to allow the ST9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism ...
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... No more than 8 routines can be nested inter- ST9+ rupt routine at level N is being serviced, no other PC, FLAGR, Interrupts located at level N can interrupt it. This CSR guarantees a maximum number of 8 nested levels including the Top Level Interrupt request. No limit Across segments ST92185B - INTERRUPTS 43/178 ...
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... If two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every ST9 version, selects the channel with the highest position in the chain, as shown in Table 5. Table 5. Daisy Chain Priority for the ST92185B Highest Position INTA0 INT0/WDT INTA1 ...
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... INT 2 CPL = 7 INT 3 CPL = 7 INT 4 CPL = 7 ST92185B - INTERRUPTS Figure INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5 MAIN CPL = 7 22) the ...
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... ST92185B - INTERRUPTS ARBITRATION MODES (Cont’d) Example 2 In the second example, (more complex, 23), each interrupt service routine sets Interrupt Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for requests with a higher priority than the one being serviced. ...
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... INT 2 INT6 CPL=2 INT 3 INT2 CPL=3 INT 4 CPL=4 CPL2 < CPL4: Serviced next ST92185B - INTERRUPTS INTERRUPT 0 HAS PRIORITY LEVEL 0 INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5 INTERRUPT 6 HAS PRIORITY LEVEL 6 INT 6 CPL=6 MAIN ...
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... ST92185B - INTERRUPTS ARBITRATION MODES (Cont’d) End of Interrupt Routine The iret Interrupt Return instruction executes the following steps: – The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system stack. – The PC high byte is popped from system stack. ...
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... PRIORITY INTB0 INT.A0: 010=2 INT.A1: 011=3 INTB1 INTC0 INT.B0: 100=4 INT.B1: 101=5 INTC1 VR000151 INTD0 INTD1 ST92185B - INTERRUPTS shows an example of priority levels. gives an overview of the External inter- Internal Interrupt External Interrupt Source Source Timer/Watchdog INT0 Standard Timer None SPI Interrupt INT2 ...
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... ST92185B - INTERRUPTS EXTERNAL INTERRUPTS (Cont’d) Figure 27. External Interrupts Control Bits and Vectors n Watchdog/Timer End of count TEA0 INT 0 pin Std. Timer Not connected SPEN,BMS TEB0 SPI Interrupt INT 2 pin ADC Not connected EOFVBI TEC0 (SYNC inter) INT 4 pin TEC1 FLDST (SYNC inter) ...
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... PRL=7: the lowest priority (the interrupt cannot be acknowledged) – Interrupt Vector Register (IVR bits). The IVR points to the vector table which itself contains the interrupt routine start address. TLIP PENDING MUX OR TLIS TLTEV ST92185B - INTERRUPTS CORE RESET TOP LEVEL INTERRUPT REQUEST MASK VA00294 51/178 ...
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... ST92185B - INTERRUPTS 3.9 INTERRUPT RESPONSE TIME The interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. One more CPUCLK cycle is required when an interrupt is acknowledged. Requests are sampled every 5 CPUCLK cycles. If the interrupt request comes from an external pin, the trigger event must occur a minimum of one INTCLK cycle before the sampling time ...
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... CICR, however in this case, take care to avoid spurious interrupts, since IEN cannot be cleared in the middle of an interrupt arbitration. Only modify ST92185B - INTERRUPTS the IEN bit when interrupts are disabled or when no peripheral can generate interrupts. For exam- ple, if the state of IEN is not known in advance, and its value must be restored from a previous push of CICR on the stack, use the sequence DI ...
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... ST92185B - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT PENDING REGISTER (EIPR) R243 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) 7 IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0 Bit 7 = IPD1: INTD1 Interrupt Pending bit Bit 6 = IPD0: INTD0 Interrupt Pending bit Bit 5 = IPC1: INTC1 Interrupt Pending bit ...
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... Watchdog End of Count is INTA0 source 1: External Interrupt pin is INTA0 source Bit 0 = EWEN: External Wait Enable. This bit is set and cleared by software. ST92185B - INTERRUPTS 0: WAITN pin disabled 1: WAITN pin enabled (to stretch the external memory access cycle). Note: For more details on Wait mode refer to the section describing the WAITN pin in the External Memory Chapter ...
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... ST92185B - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0000 1111 (0Fh ENCSR Bit 7, 5:0 = Reserved, keep in reset state. Refer to the external Memory Interface Chapter. Bit 6 = ENCSR: Enable Code Segment Register. This bit is set and cleared by software. It affects the ST9 CPU behaviour whenever an interrupt re- quest is issued ...
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... Figure 29. Reset Overview n RESET RESETO ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU) – A Watchdog end of count. The RESET input is schmitt triggered. Note: The memorized Internal Reset (called RE- SETO) will be maintained active for a duration of 32768 Oscin periods (about 8 ms for a 4 MHz crys- tal) after the external input is released (set high) ...
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... ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU) 4.3 OSCILLATOR CHARACTERISTICS The on-chip oscillator circuit uses an inverting gate circuit with tri-state output. Notes: Owing to the Q factor required, Ceramic Resonators may not provide a reliable oscillator source . The oscillator can not support quartz crystal or ce- ramic working at the third harmonic without exter- nal tank circuits ...
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... C1,C2: maximum total capacitance on pins OS- CIN/OSCOUT (value including external capaci- tance tied to the pin plus the parasitic capacitance of the board and device). ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU) Table 9. Crystal Specification (C0 Legend: Rs: Parasitic Series Resistance of the quartz crystal (up- per limit) C0: Parasitic capacitance of the quartz crystal (upper limit, < ...
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... ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU) 4.4 CLOCK CONTROL REGISTERS MODE REGISTER (MODER) R235 - Read/Write Register Group: E (System) Reset Value: 1110 0000 (E0h DIV2 PRS2 PRS1 Bit 7:6 = Bits described in Device Architecture chapter. Bit 5 = DIV2: OSCIN Divided This bit controls the divide by 2 circuit which oper- ates on the OSCIN Clock ...
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... RCCU PLL and CSDU are turned off when a HALT instruction is performed. 1: RCCU will reset the microcontroller when a HALT instruction is performed. Bit 6:0= Reserved bits. Leave in their reset state. ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK SLOW DOWN UNIT RATIO REGISTER (SDRATH) R254 - Read/Write Register Page: 55 ...
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... ST92185B - TIMING AND CLOCK CONTROLLER 5 TIMING AND CLOCK CONTROLLER 5.1 FREQUENCY MULTIPLIERS Three on-chip frequency multipliers generate the proper frequencies for: the Core/Real time Periph- erals, the Display related time base. Figure 33. Timing and Clock Controller Block Diagram PXFM Frequency Multiplier Async. ...
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... Table 12. External PLL Filter Stabilisation time Clock Pin Name MCFM Main Clock PLL Filter Input Pin PXFM Pixel Clock PLL Filter Input Pin ST92185B - TIMING AND CLOCK CONTROLLER 4 MHz 4 MHz 4 MHz 4 MHz 4 MHz Note: 24 MHz is the max. CPU authorized frequency. Table 11. DOTCK/2 frequency choices ...
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... ST92185B - TIMING AND CLOCK CONTROLLER Figure 34. Programming the MCCR Set the PLL frequency FML (3:0) Start the PLL by setting FMEN = 1 Wait for Clock Stabilization Validate PLL as Main CPU Clock Figure 35. Programming the SKCCR, PXCCR Set the PLL frequency SKW (3:0) Start the PLL by setting ...
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... Frequency Multiplier which generates the internal multiplied frequency Fimf. The Fimf value is calculated as follows : Fimf = Crystal frequency * [ (FML(3: ST92185B - TIMING AND CLOCK CONTROLLER SKEW CLOCK CONTROL REGISTER (SKCCR) R254 - Read/ Write Register Page: 39 Reset value: 0000 0000 (00h) ...
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... ST92185B - TIMING AND CLOCK CONTROLLER REGISTER DESCRIPTION (Cont’d) PLL CLOCK CONTROL REGISTER (PXCCR) R251 - Read/Write Register Page: 39 Reset value: 0000 0000 (00h PXCE Bit 7= PXCE. Pixel Clock Enable bit. 0: Pixel and TDSRAM interface clocks are blocked 1: Pixel clock is sent to the display controller and TDSRAM interface ...
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... F9h P2C1 F8h P2C0 F7h Reserved F6h P1C2 F5h P1C1 F4h P1C0 F3h Reserved F2h P0C2 F1h P0C1 F0h P0C0 ST92185B - I/O PORTS GROUP F GROUP F PAGE 3 PAGE 43 P7DR P9DR R255 P7C2 P9C2 R254 P7C1 P9C1 R253 P7C0 P9C0 R252 P6DR P8DR R251 ...
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... ST92185B - I/O PORTS PORT CONTROL REGISTERS (Cont’d) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 and 1 in ROM- less devices, and can be redefined under software control ...
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... BID OUT OUT HI-Z TTL TTL TTL CMOS (or Schmitt (or Schmitt (or Schmitt (or Schmitt Trigger) Trigger) Trigger) Trigger) ST92185B - I/O PORTS PxC20 PxC10 PxC00 OUT AF OUT HI TTL TTL TTL (or Schmitt (or Schmitt (or Schmitt ...
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... ST92185B - I/O PORTS INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 38. Basic Structure of an I/O Port Pin PUSH-PULL TRISTATE OPEN DRAIN WEAK PULL-UP OUTPUT SLAVE LATCH ALTERNATE FROM FUNCTION PERIPHERAL OUTPUT INPUT OUTPUT BIDIRECTIONAL OUTPUT MASTER LATCH Figure 39. Input Configuration I/O PIN TRISTATE OUTPUT SLAVE LATCH ...
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... Function Output: (Figure 7) – The Output Buffer is turned Open-Drain or Push-Pull configuration. ST92185B - I/O PORTS – The data present on the I/O pin is sampled into the Input Latch at the beginning of the execution of the instruction. – The signal from an on-chip function is allowed to load the Output Slave Latch driving the I/O pin. ...
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... ST92185B - I/O PORTS 6.5 ALTERNATE FUNCTION ARCHITECTURE Each I/O pin may be connected to three different types of internal signal: – Data bus Input/Output – Alternate Function Input – Alternate Function Output 6.5.1 Pin Declared as I/O A pin declared as I/O, is connected to the I/O buff- er. This pin may be an Input, an Output bidi- rectional I/O, depending on the value stored in (PxC2, PxC1 and PxC0) ...
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... HW0SW1 MUX WDGEN 1 Pin not present on some ST9 devices ST92185B - TIMER/WATCHDOG (WDT) The main WDT registers are: – Control register for the input, output and interrupt logic blocks (WDTCR) – 16-bit counter register pair (WDTHR, WDTLR) – Prescaler register (WDTPR) The hardware interface consists five sig- nals: – ...
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... ST92185B - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 7.1.2 Functional Description 7.1.2.1 External Signals The HW0SW1 pin can be used to permanently en- able Watchdog mode. Refer to The WDIN Input pin can be used in one of four modes: – Event Counter Mode – Gated External Input Mode – Triggerable Input Mode – ...
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... PWM signals by modifying the status of the WROUT pin between End of Count events, based on software counters decre- mented by the Timer Watchdog interrupt. ST92185B - TIMER/WATCHDOG (WDT) 7.1.3 Watchdog Timer Operation This mode is used to detect the occurrence of a software fault, usually generated by external inter- ...
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... ST92185B - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 7.1.3.3 Preventing Watchdog System Reset In order to prevent a system reset, the sequence AAh, 55h must be written to WDTLR (Watchdog Timer Low Register). Once 55h has been written, the Timer reloads the constant and counting re- starts from the preset value. ...
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... Legend: WDG = Watchdog function SW TRAP = Software Trap Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0 interrupts), only the INTA0 interrupt is taken into account. ST92185B - TIMER/WATCHDOG (WDT) Figure 46. Interrupt Sources INT0 NMI Enabled Sources ...
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... ST92185B - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 7.1.5 Register Description The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File. WDTHR: Timer/Watchdog High Register WDTLR: Timer/Watchdog Low Register WDTPR: Timer/Watchdog Prescaler Register WDTCR: Timer/Watchdog Control Register Three additional control bits are mapped in the fol- lowing registers on Page 0: Watchdog Mode Enable, (WCR ...
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... Bit 6 = WDGEN: Watchdog Enable (active low). Resetting this bit via software enters the Watch- dog mode. Once reset, it cannot be set anymore ST92185B - TIMER/WATCHDOG (WDT) by the user program. At System Reset, the Watch- dog mode is disabled. Note: This bit is ignored if the Hardware Watchdog option is enabled by pin HW0SW1 (if available) ...
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... ST92185B - STANDARD TIMER (STIM) 7.2 STANDARD TIMER (STIM) Important Note: This chapter is a generic descrip- tion of the STIM peripheral. Depending on the ST9 device, some or all of the interface signals de- scribed may not be connected to external pins. For the list of STIM pins present on the particular ST9 device, refer to the pinout description in the first section of the data sheet ...
Page 81
... Standard Timer Input STIN) Bits INMD2, INMD1 and INEN are used to select the input modes. The Input Enable (INEN) bit ena- ST92185B - STANDARD TIMER (STIM) bles the input mode selected by the INMD2 and INMD1 bits. If the input is disabled (INEN="0"), the values of INMD2 and INMD1 are not taken into ac- count ...
Page 82
... ST92185B - STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 7.2.2.4 Standard Timer Output Modes OUTPUT modes are selected using 2 bits of the STC register: OUTMD1 and OUTMD2. No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”) The output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the I/O pin. Square Wave Output Mode (OUTMD1 = “ ...
Page 83
... When reading the STP register, the returned value corresponds to the programmed data instead of the current data. 00h: No prescaler 01h: Divide by 2 FFh: Divide by 256 ST92185B - STANDARD TIMER (STIM) STANDARD (STC) R243 - Read/Write Register Page: 11 Reset value: 0001 0100 (14h) ...
Page 84
... ST92185B - DISPLAY STORAGE RAM INTERFACE 7.3 DISPLAY STORAGE RAM INTERFACE 7.3.1 Introduction The Display RAM (TDSRAM) is used to hold the OSD data for display. It can be shared by the following units: – Display Unit (DIS). This OSD generator is de- scribed in a separate chapter. – CPU accesses for control. ...
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... CPU (only in case of direct CPU access) and one of the hardware units, the CPU automatically enters a "wait" configuration until its request is serviced. ST92185B - DISPLAY STORAGE RAM INTERFACE 7.3.2.1 TV Line Timesharing During a TV line, to maintain maximum perform- ance, a continuous cycle is run repetitively. This cycle is divided in 8 sub-cycles called " ...
Page 86
... ST92185B - DISPLAY STORAGE RAM INTERFACE TDSRAM (Cont’d) 7.3.3 Initialisation 7.3.3.1 Clock Initialisation Before initialising the TRI, first initialise the pixel clock. Refer to the Application Examples in the OSD chapter and to the RCCU chapter for a de- scription of the clock control registers. 7.3.3.2 TRI Initialisation It is recommended to wait for a stable clock issued from the Pixel frequency multiplier before enabling the TDSRAM interface ...
Page 87
... Bit 7:2 = Reserved, keep in reset state. ST92185B - DISPLAY STORAGE RAM INTERFACE Bit 1 = DON: Display ON/OFF . 0: No display reading allowed (display slot com- pletely used for CPU access). 1: Display reading enabled during the respective access slot. Note: DON can be changed only when the TRI is off (GEN = 0) ...
Page 88
... ST92185B - ON SCREEN DISPLAY (OSD) 7.4 ON SCREEN DISPLAY (OSD) 7.4.1 Introduction The OSD displays Teletext or other character data and menus screen. In serial mode, characters are coded on one byte. The display is fully compliant with the WST Tele- text level 1.5. In parallel mode, characters are coded on two ...
Page 89
... Translucency: OSD background color mixed with video picture. – Full screen Color (15) Mode Triple G0 Single G0 ST92185B - ON SCREEN DISPLAY (OSD) – National Character set selection – National Character mode selection – Global Double Height display (Zooming Func- tion) – Global Fringe Enable – ...
Page 90
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Figure 49. Display Block Diagram Row Counter Comp 10/20 Line Counter Scroll N Row SCROLLING Scroll 1 Row CONTROL Gen PLA Cmd MOSAIC PLA Shift Register (10b) L1/L1+ mux Char Decoding Character Code RAM INTERFACE 90/178 RAM INTERFACE ...
Page 91
... Definition of Displayed Areas 26 LINES (TEXT PAGE) Figure 51. Screen Display Area. ST92185B - ON SCREEN DISPLAY (OSD) The three special rows, a Header and two Status rows have specific meanings and behaviour. They are always displayed the same way (40 charac- ters) and at the same place. In these rows, size at- tributes, scrolling and 80-character modes are not allowed ...
Page 92
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.3.2 Color Processing The color of any pixel on screen is the result of a priority processing among several layers which are (going from the lowest priority to the highest one): Full Screen Color where nothing is processed Default Background Color (it assumes pixel is ...
Page 93
... Figure 52. Display Character scheme ROUNDING MODE Background Foreground Smooth Rounding Figure 53. Rounding and Fringe Effects Dot (four pixels) Added pixel Smooth Rounding Effect ST92185B - ON SCREEN DISPLAY (OSD) NORMAL MODE Underline Added pixel Global Rounding Effect FRINGE MODE Background Foreground Fringe VR02112B ...
Page 94
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.4 Programming the Display All the characteristics of the display are managed by programmable attributes: Global Attributes Serial Attributes Parallel Attributes (active until a superseding serial or parallel attribute). Table 15. Global Attributes Global Attributes 0= Display Off (Default) Display Enable (DE) ...
Page 95
... Foreground default color are defined for the displayed row. These default colors are selected at each beginning of a line and are defined by means of the corresponding register. Full screen color Color displayed outside of the vertical display area. ST92185B - ON SCREEN DISPLAY (OSD) Description Control Register FSCCR ...
Page 96
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Figure 54. Semi-Transparent Display Scheme and Fast Blanking Behaviour NORMAL DISPLAY LINE 3 NORMAL DISPLAY CKPIX LINE 4 NORMAL DISPLAY CKPIX Figure 55. Translucent Display Scheme CKPIX R, G, B(40c) FB TSLU 96/178 Fringe line 3 Field odd ...
Page 97
... ON SCREEN DISPLAY (Cont’d) Figure 56. Half-Tone Display Scheme VIDEO PROCESSOR Internal Red Contrast Internal Green Reduction Internal Blue HT ST92185B - ON SCREEN DISPLAY (OSD) RGB Switch ST9 MCU Rout Gout Bout 97/178 ...
Page 98
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.4.2 Row Attributes The header and status row attributes are set using the HSCR R244 (F4h) Page 32 register. The row enable bits as set in registers DE0R .. 2 R253 ..255 Page 32. Header Enable When the display is in line mode, row 0, called the header, is also usable ...
Page 99
... DCM0R R250 (FAh) Page 32. Boxing: A part of the page (where this bit is active) is inserted in a specific window depending on 3 control bits defined in the FSCCR register. (see Figure 11) ST92185B - ON SCREEN DISPLAY (OSD) 00001 00010 Foreground Color (Mosaic Chars) Flash Black (3) ...
Page 100
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Figure 59. Example of Boxing Attribute in Serial Mode Display Default background Memory location Default foreground *Depending on FSCCR Figure 60. Example of Double Height Attribute in Serial Mode Display Memory Location ...
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... The attribute can be one of two types defined by most significant bit (PS): – Color attribute – Shape attribute US: Underline / Separate Mosaic graphics (see above). DH: Double Height: The half character is displayed in the current row depending on the Upper Height ST92185B - ON SCREEN DISPLAY (OSD ...
Page 102
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Table 18. Parallel Color and Shape Attributes. BIT NAME FUNCTION 0 BR Background Red 1 BG Background Green 2 BB Background Blue 3 HI Half-Intensity 4 FR Foreground Red 5 FG Foreground Green 6 FB Foreground Blue 7 PS= 0 Parallel Attribute Selection ...
Page 103
... Display with CSSn-2 CSSn-1 Stored CSS CSSn-2 CSSn-2 ST92185B - ON SCREEN DISPLAY (OSD) CSS has two kinds of behaviour: – set once, the CSS attribute is applied on the current character only. – set twice, the CSS of the first character with PS=1 is propagated. Note: The value stored as a preceding CSS value is forced when alpha or mosaic color serial at- tributes are used ...
Page 104
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Figure 63. Parallel Mode Display Example 1 Showing Character and Attribute Byte Pairs: Characters New Foreground (Serial Attribute Serial Attribute Parallel Mode Display Example 2: M 104/178 RAM content in Parallel Mode ...
Page 105
... Double width Double width Attributes location Characters location ST92185B - ON SCREEN DISPLAY (OSD) 7.4.4.6 Attribute In parallel mode, double width on character can be obtained using the following rule It is important to set Double Width (bit 3 of the shape attribute) on the current character attribute and Single Size on the following one. The second character location can be either a serial attribute or another character ...
Page 106
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.4.7 Example of using Double Height Attribute In parallel mode, Double Height characters can be obtained as follows. The Double Height attribute concerns two consecutive rows. Repeat the char- Figure 65. Double Height Example Double height Display Previous/default color ...
Page 107
... The character to magnify must Figure 66. Double Size Examples Display Attribute location Character location ST92185B - ON SCREEN DISPLAY (OSD) be repeated on the two rows. Bits 2 and 3 of the shape attribute must be set on the two locations. In addition bit 4 must be set or reset to define the top or bottom half-character. A Double size ...
Page 108
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.4.9 Example of using Underline Attribute In parallel mode, the Underline mode on character can be obtained simply by setting the bit 1 ‘US’ of the shape attribute. To underline double height Figure 67. Underline Example Display Attribute location Underline (US=1) Character location ...
Page 109
... In parallel mode, the double height (bit 2 of the shape attribute) is active only on its own char- acter. Setting one double height attribute does ST92185B - ON SCREEN DISPLAY (OSD) not cover the following characters of the row (different from double height in serial mode). Figure 68. Rule for Serial and Parallel Color ...
Page 110
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.4.11 Cursor Control Horizontal position (by character) Vertical position (by row) Color or Underline Cursor Modes Color Cursor with inverted foreground / inverted background Flash or Steady mode Color Cursor Cursor display is controlled using two registers: – Cursor Horizontal Position R246 (F6h) Page 32 – ...
Page 111
... Figure 70. Serial Mode (40 Characters) - Header and Status Mapping 0.5K TDSRAM Header Status Row 0 Status Row 1 Free Space Resolution 0.5K bytes ST92185B - ON SCREEN DISPLAY (OSD) 7.4.6.1 Building a Serial Mode Full Page 40- Char Display Page Location: The 1 Kbyte block of page content is stored in the TDSRAM location pointed to by the PG3..PG0 bits. ...
Page 112
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.6.2 Building a Parallel Mode, 40-Char, Full Page Display Page Location: The pair of adjacent 1 Kbyte blocks of page con- tent is stored in the TDSRAM location pointed to by the PG3..PG0 bits. The first block contains the characters, the second block contains the attribute bytes ...
Page 113
... Number Row 11 Row 12/ Scrolling Buffer Free Space Resolution 0.5K bytes ST92185B - ON SCREEN DISPLAY (OSD) Header & Status Rows Location: The 0.5 Kbyte block containing the Header, Status Row 0 and Status Row 1 is pointed to by the HS3..HS0 bits. The Row attribute (row count) is ...
Page 114
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.6.4 Building a Parallel Mode, 40 Char, Line mode Display Half-Page Location: The pair of adjacent 0.5 Kbyte blocks of half page content is stored in the TDSRAM location pointed to by the PG3..PG0 bits. One block contains the characters, the other block contains the attribute bytes ...
Page 115
... Scrolling Buffer Free Space Resolution 2K bytes See Figure 23 for Address Values ST92185B - ON SCREEN DISPLAY (OSD) Header & Status Rows Location: The 0.5 Kbyte block containing the Header, Status Row 0 and Status Row 1 is pointed to by the HS3..HS0 bits. Row Scrolling Buffer Location: ...
Page 116
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.6.6 Building a Serial Mode, 80 Char, Line Mode Display Half-Page Location: The pair of 0.5 Kbyte blocks of half page content is stored in the TDSRAM location pointed to by the PG3..PG0 bits. The first block contains the left half rows, the other block contains the right half rows ...
Page 117
... Character set selection is done by four bits (NC1:0 or NC3:2) in the NCSR register R245 (F5h) Page 32. ST92185B - ON SCREEN DISPLAY (OSD) – In Serial Mode (Level 1), only 256 Character Codes are available using an 8-bit code. The character codes plus some serial attributes and ...
Page 118
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Table 22. National Character Subset Mapping (Ordered by their G0 address) 1st 2nd 3rd 4th 23h 24h 40h 5Bh 5Ch 8th 9th 10th 11th 12th 5Fh 60h 7Bh 7Ch 7Dh Figure 78. Font Mapping Addresses 0 1F SERIAL ...
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... Portugese/ Spanish Rumanian Serbian/ Croatian/ Slovenian Swedish/ Finnish Turkish ST92185B - ON SCREEN DISPLAY (OSD) CSS Font Usage 1 Extended menu G0 + National Character Subset 0 (96 chars Menu (128 chars) National Character Subset 1 (13 chars) National Character Subset 2 (13 chars) National Character Subset 3 (13 chars) ...
Page 120
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Figure 79. Pan-European Font (East/West) Character Codes (Hex.) National Character Subset 0 Figure 80. OSD Picture in Parallel Mode 120/178 Extended Menu G0_0 G2-Menu National Char. Subsets 1..14d Extended Menu ...
Page 121
... Hsync by HP[7:0]. The first character display starts when the counter turns to zero. Hori delay= [(HP7*128 + HP6*64 + HP5*32 + HP4*16 + HP3*8 + HP2*4 + HP1*2 + HP0) * Tpix] + Thblank ST92185B - ON SCREEN DISPLAY (OSD) VERTICAL POSITION REGISTER (VPOSR) R242 - Read/Write Register Page: 32 Reset Value: 0000 0000 (00h) ...
Page 122
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) FULL SCREEN COLOR CONTROL REGISTER (FSCCR) R243 - Read/Write Register Page: 32 Reset Value: 0000 0000 (00h TIO MM HTC FSC3 Bit 7 = BE: Box Enable, see Table Bit 6 = TIO: Text out/not in, see Bit 5 = MM: Mixed Mode, see ...
Page 123
... Status Row is filled with the full screen color; if the bit is set, the corresponding Status Row is dis- played (Status Row 1 is assumed to be the bottom one). ST92185B - ON SCREEN DISPLAY (OSD) Bit 4,2 = NS[1:0]: Serial/Parallel Mode Status Rows display control bits . If the corresponding bit is reset, the Status Row uses only serial attributes. ...
Page 124
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) NATIONAL CHARACTER SET REGISTER (NCSR) R245 - Read/Write Register Page: 32 Reset Value: 0000 0000 (00h) 7 TSLE 0 SWE NCM NC3 The register bit values are sampled and then acti- vated only at each field start (on Vsync pulse). ...
Page 125
... CVP4 CVP3 CVP2 CVP1 CVP0 Bit 7 = FON: "Flash On" flag bit. The FON bit remains at "0" during 32 consecutive ST92185B - ON SCREEN DISPLAY (OSD) TV fields followed by a "1" state during the 16 next TV fields. This flag provides a 1Hz time reference for an easy software control of all flashing effects (assuming signal, the FON total period will be 0 ...
Page 126
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) SCROLLING CONTROL LOW (SCLR) R248 - Read/Write Register Page: 32 Reset Value: 0000 0000 (00h) 7 SCE FSC SS FRS4 FRS3 Bit 7 = SCE: Scrolling Enable Before enabling scrolling, the scrolling area must be defined by the FRS[4:0] and LRS[4:0] bits. The scrolling direction is defined by the UP/D bit ...
Page 127
... To avoid this effect remove the serial double height attribute from row 23. ST92185B - ON SCREEN DISPLAY (OSD) REGISTER Bit 6 = EER: End of Extra Row flag bit. This bit is forced to "1" by hardware when the last line of the extra row is displayed in case of scroll- ing in normal height ...
Page 128
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Figure 82. Memory Management for Scrolling Window Freeze off after 5 Vsync Normal Height ROW A T0 ROW B 3 rows to be scrolled ROW C ROW A ROW VSYNC ROW C ROW D ROW B ROW VSYNC ROW D ROW A ROW B ...
Page 129
... G0 Toggle Bit 4 = CE: Conceal Enable control bit . 0: Reveal any text defined as concealed by serial attributes (Default) ST92185B - ON SCREEN DISPLAY (OSD) 0 REGISTER 1: Conceal any text defined as concealed by serial attributes Bit 3 = GFR: Global Fringe Enable control bit. If this bit is set, the whole display is in fringe mode ...
Page 130
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) DISPLAY CONTROL MODE (DCM1R) R251 - Read/Write Register Page: 32 Reset Value: 0000 0000 (00h EXTF Bit 7:4 = Reserved bits, keep in reset state. Bit 3 = EXTF: External Font. Only when the emulator is used, this bit selects the font memory containing a user-defined OSD font ...
Page 131
... When the “Ri” bit is set (Reset value), the corre- sponding row (with row in the page, numbered from 1 to 23) will be displayed. When the “Ri” bit is reset, the full screen color is displayed. ST92185B - ON SCREEN DISPLAY (OSD) DISPLAY ENABLE 2 CONTROL REGISTER (DE2R) R255 -Read/Write ...
Page 132
... ST92185B - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) DEFAULT COLOR REGISTER (DCR) R240 - Read/Write Register Page: 33 Reset Value: 0111 0000 (70h) 7 DFG3 DFG2 DFG1 DFG0 DBG3 DBG2 DBG1 DBG0 Bit 7:4 = DFG[3:0]: Default Foreground Color. DFG[3:0] = (Half-Intensity Bit 3:0 = DBG[3:0]: Default Background Color ...
Page 133
... Timings & clock Controller registers page ; set page pointer to page 39 decimal ld SKCCR, #0x09; FE, Skew clock control register ; program the frequency multiplier down ; counter in the feed-back loop ST92185B - ON SCREEN DISPLAY (OSD) provided by the freq. multplier ; set page pointer to page 23h or 35 decimal 133/178 ...
Page 134
... ST92185B - ON SCREEN DISPLAY (OSD) ; dot_freq= 4Mhz(4+1)=20Mhz (4/3) ; dot_freq= 4Mhz(5+1)=24Mhz (16/9) ; divide SKCCR, #0x89; enable the freq. multiplier srp #BK20 ldw rr0,#0x0FFF; time_stab2: ; for frequency multiplier stabilization decw rr0; SKEW clock stabilization cpw rr0,#0x00 ; jxnz time_stab2; ld PXCCR,#0x80;(PXCCR) spp #TDSR_PG2 ...
Page 135
... Display memory map registers page ld DC, #07Fh ; reg. F0h, DFG [3:0], DBG [3: full white ; BG grey (half white) ;----------------------------- spp #DMP1_PG; page 020h Display memory map registers page ld DE0R, #0FFh; ROWEN [8:1] ld DE1R, #0FFh; ROWEN [16:9] ld DE2R, #0FFh; ROWEN [23:17] ret ======================================================================= ST92185B - ON SCREEN DISPLAY (OSD) 135/178 ...
Page 136
... ST92185B - SYNC CONTROLLER 7.5 SYNC CONTROLLER The SYNC Controller receives Horizontal / Vertical sync information coming from the chassis. The VSYNC and HSYNC inputs use schmitt triggers to guarantee sufficient noise rejection. The SYNC Controller unit provides the H internal sync signal to the Display Skew Corrector, which rephases the Pixel clock ...
Page 137
... It must be cleared by software. The second interrupt appears at the end of each Vertical Blank Interval generated at the begin- ST92185B - SYNC CONTROLLER ning of the line 25 counted from the deflection cir- cuitry (i.e. from VSYNC); and is called the “End OF VBI” interrupt. A flag is associated to this interrupt, called “ ...
Page 138
... ST92185B - SYNC CONTROLLER SYNC CONTROLLER (Cont’d) 7.5.4.2 Composite Sync Input Mode This mode is very similar to the “Standard Sync In- put Mode” described above also accessed when both MOD1 and MOD0 bits are reset. In Composite Sync mode, a single CSYNC/ HSYNC input pin is used to enter both the horizon- tal and vertical sync pulses (VSEP control bit is set to 1) ...
Page 139
... TV Field” configuration is generated. 1st TV Field 625 525 2nd TV Field d1 313 314 315 316 263 264 265 266 ST92185B - SYNC CONTROLLER 4 5 (50 Hz Mode) 6 (60 Hz Mode 4.75 µ 2.25 µs d2 (50 Hz Mode) 319 317 318 (60 Hz Mode) 269 267 268 VR02092C ...
Page 140
... ST92185B - SYNC CONTROLLER SYNC CONTROLLER (Cont’d) 7.5.5 Register Description SYNC CONTROLLER CONTROL AND STATUS REGISTER 0 (SCCS0R) R242 - Read/Write Register Page: 35 Reset value: 0000 0000 (00h) VPOL HPOL VSEP VDLY HSF3 HSF2 Bit 7= VPOL. VSYNC Polarity When MOD[1:0] are reset, this bit configures the polarity of the VSYNC input ...
Page 141
... This bit is read-only. It indicates which field is cur- rently running; 0: First field is running 1: Second field is running n ST92185B - SYNC CONTROLLER Bit 4= HFLG: Horizontal Sync Flag . This bit is read-only. It just copies the Horizontal sync transient information issued by the horizontal pulse shape unit. The bit is read at “1” at during each H sync pulse and lasts to “ ...
Page 142
... ST92185B - SERIAL PERIPHERAL INTERFACE (SPI) 7.6 SERIAL PERIPHERAL INTERFACE (SPI) 7.6.1 Introduction The Serial Peripheral Interface (SPI general purpose on-chip shift register peripheral. It allows communication with external peripherals via an SPI protocol bus. In addition, special operating modes allow re- duced software overhead when implementing I bus and IM-bus communication standards ...
Page 143
... Bus protocol are open-drain to allow arbitration and multiplexing. Figure 2 below shows a typical SPI network. Figure 87. A Typical SPI Network n ST92185B - SERIAL PERIPHERAL INTERFACE (SPI) 7.6.3.1 Input Signal Description Serial Data In (SDI) Data is transferred serially from a slave to a mas- ter on this line, most significant bit first ...
Page 144
... ST92185B - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 88. SPI I/O Pins n SCK SDO SDI PORT BIT LATCH PORT BIT LATCH PORT BIT LATCH INT2 144/178 7.6.4 Interrupt Structure The SPI peripheral is associated with external in- terrupt channel B0 (pin INT2). Multiplexing be- ...
Page 145
... SDI is from During both of these conditions, if SPEN = 0 and BMS = 1 then an interrupt request is performed. ST92185B - SERIAL PERIPHERAL INTERFACE (SPI) Each transmission consists of nine clock pulses (SCL line). The first 8 pulses transmit the byte (MSB first), the ninth pulse is used by the receiver to acknowledge ...
Page 146
... ST92185B - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 2 Table 28. Typical I C-bus Sequences Phase SPICR.CPOL, CPHA = 0, 0 SPICR.SPEN = 0 SPICR.BMS = 1 INITIALIZE SCK pin set as AF output SDI pin set as input Set SDO port bit to 1 SDO pin set as output START Open Drain Set SDO port bit to 0 SPICR ...
Page 147
... ST9-2-SCK 1 ST9-1-SCK ST92185B - SERIAL PERIPHERAL INTERFACE (SPI) ferent clock sources and different frequencies can be interfaced. Arbitration Lost When several masters are sending data on the SDA line, the following takes place: if the transmit- ter sends a “1” and the SDA line is forced low by Figure 4) ...
Page 148
... ST92185B - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 7.6.7 S-Bus Interface The S-bus is a three-wire bidirectional data-bus, possessing functional features similar to the I 2 bus. As opposed to the I C-bus, the Start/Stop conditions are determined by encoding the infor- mation on 3 wires rather than shown in Figure 8 ...
Page 149
... CLOCK LINE 2 DATA LINE LSB 1 ST92185B - SERIAL PERIPHERAL INTERFACE (SPI) line is set to the Open-Drain configuration, the in- coming data bits that are set to “1” do not affect the (Fig- SDO/SDI line status (which defaults to a high level due to the FFh value in the transmit register), while incoming bits that are set to “ ...
Page 150
... ST92185B - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 7.6.9 Register Description It is possible to have independent SPIs in the same device (refer to the device block dia- gram). In this case they are named SPI0 thru SPI2. If the device has one SPI converter it uses the register adresses of SPI0 ...
Page 151
... CPOL CPHA ( Figure 96. SPI Data and Clock Timing ST92185B - SERIAL PERIPHERAL INTERFACE (SPI) Bit 1:0 = SPR[1:0]: SPI Rate. These two bits select one (of four) baud rates used as SCK. SPR1 SPR0 0 shows the relation SCK Figure 11) ...
Page 152
... ST92185B - A/D CONVERTER (A/D) 7.7 A/D CONVERTER (A/D) 7.7.1 Introduction The 8 bit Analog to Digital Converter uses a fully differential analog configuration for the best noise immunity and precision performance. The analog voltage references of the converter are connected to the internal AV & AV analog supply pins the chip if they are available, otherwise to the ordi- ...
Page 153
... ST92185B - A/D CONVERTER (A/D) These events can be enabled or masked by pro- gramming the TRG bit in the ADCLR Register. The effect of alternate synchronization is to set the STR bit, which is cleared by hardware at the end of each conversion in single mode ...
Page 154
... ST92185B - A/D CONVERTER (A/D) A/D CONVERTER (Cont’d) 7.7.4 Register Description A/D CONTROL LOGIC REGISTER (ADCLR) R241 - Read/Write Register Page: 62 Reset value: 0000 0000 (00h TRG POW CONT STR This 8-bit register manages the A/D logic opera- tions. Any write operation to it will cause the cur- rent conversion to be aborted and the logic to be re-initialized to the starting configuration ...
Page 155
... Reset value: undefined 7 R.7 R.6 R.5 R.4 R.3 The result of the conversion of the selected chan- nel is stored in the 8-bit ADDTR, which is reloaded with a new value every time a conversion ends. Bit 7:0 = R[7:0]: Channel i conversion result . ST92185B - A/D CONVERTER (A/D) A/D INTERRUPT REGISTER (ADINT) Register Page: 62 R242 - Read/write Reset value: 0000 0001 (01h R.2 R.1 R Bit 7:1 = Reserved ...
Page 156
... ST92185B - VOLTAGE SYNTHESIS TUNING CONVERTER (VS) 7.8 VOLTAGE SYNTHESIS TUNING CONVERTER (VS) 7.8.1 Description The on-chip Voltage Synthesis (VS) converter al- lows the generation of a tuning reference voltage set application. The peripheral is com- posed of a 14-bit counter that allows the conver- sion of the digital content in a tuning voltage, avail- ...
Page 157
... ST92185B - VOLTAGE SYNTHESIS TUNING CONVERTER (VS) VOLTAGE SYNTHESIS (Cont’d) PWM Generation The counter increments continuously, clocked at INTCLK divided by 4. Whenever the 7 least signif- icant bits of the counter overflow, the VS output is set. The state of the PWM counter is continuously compared to the value programmed in the 7 most significant bits of the tuning word ...
Page 158
... ST92185B - VOLTAGE SYNTHESIS TUNING CONVERTER (VS) VOLTAGE SYNTHESIS (Cont’d) Figure 100. PWM Simplified Voltage Output After Filtering (2 examples PWMOUT OUTPUT VOLTAGE 0V "CHARGE" PWMOUT OUTPUT VOLTAGE 0V "CHARGE" "DISCHARGE" 158/178 "DISCHARGE" "CHARGE" "CHARGE" "DISCHARGE" V ripple (mV) V OUTAVG "DISCHARGE" V (mV) ...
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... ST92185B - VOLTAGE SYNTHESIS TUNING CONVERTER (VS) VOLTAGE SYNTHESIS (Cont’d) BRM Generation The BRM bits allow the addition of a pulse to wid standard PWM pulse for specific PWM cy- cles. This has the effect of “fine-tuning” the PWM Duty cycle (without modifying the base duty cycle), thus, with the external filtering, providing additional fine voltage steps ...
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... ST92185B - VOLTAGE SYNTHESIS TUNING CONVERTER (VS) VOLTAGE SYNTHESIS (Cont’d) 7.8.3 Register Description VS DATA AND CONTROL (VSDR1) R254 - Read/Write Register Page: 59 Reset Value: 0000 0000 (00h VSE VSWP VD13 VD12 VD11 Bit 7 = VSE: VS enable bit Tuning Converter disabled (i.e. the clock is ...
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... Compare 5 Compare 4 Compare 3 Compare 2 Compare 1 Compare 0 ST92185B - PWM GENERATOR quency range from 1465 23437 Hz can be achieved. Higher frequencies, with lower resolution, can be achieved by using the autoclear register ex- ample, with a 12 MHz Internal clock, a maximum PWM repetition rate of 93750 Hz can be reached with 6-bit resolution ...
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... ST92185B - PWM GENERATOR PWM GENERATOR (Cont’ PWM outputs can be selected as Alternate Functions of an I/O port. Each output bit is inde- pendently controlled by a separate Compare Reg- ister. When the value programmed into the Com- pare Register and the counter value are equal, the corresponding output bit is set ...
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... R243 - Read/Write Register Page: 59 Reset Value: 0000 0000 (00h) 7 CM3.7 CM3.6 CM3.5 CM3.4 CM3.3 CM3.2 CM3.1 CM3.0 This is the compare register controlling PWM out- put 3. ST92185B - PWM GENERATOR COMPARE REGISTER 4 (CM4) R244 - Read/Write Register Page: 59 Reset Value: 0000 0000 (00h CM4.7 CM4.6 CM4.5 CM4.4 CM4.3 CM4.2 CM4.1 CM4.0 This is the compare register controlling PWM out- put 4 ...
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... ST92185B - PWM GENERATOR PWM GENERATOR (Cont’d) AUTOCLEAR REGISTER (ACR) R248 - Read/Write Register Page: 59 Reset Value: 1111 1111 (FFh) 7 AC7 AC6 AC5 AC4 AC3 This register behaves exactly as a 9th compare Register, but its effect is to clear the CRR counter register, so causing the desired PWM repetition rate ...
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... Bit 4 = OCPL.4: Complement PWM Output 4. Bit 3 = OCPL.3: Complement PWM Output 3. Bit 2 = OCPL.2: Complement PWM Output 2. Bit 1 = OCPL.1: Complement PWM Output 1. Bit 0 = OCPL.0: Complement PWM Output 0. ST92185B - PWM GENERATOR OUTPUT ENABLE REGISTER (OER) R252 - Read/Write Register Page: 59 Reset Value: 0000 0000 (00h) ...
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... ST92185B - ELECTRICAL CHARACTERISTICS 8 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage DD V Analog Ground SSA V Analog Supply Voltage DDA V Input Voltage I V Analog Input Voltage (A/D Converter Output Voltage O T Storage Temperature STG Pin Injected Current I Maximum Accumulated Pin INJ Injected Current In Device Note: Stress above those listed as “ ...
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... I I/O pin input leakage current LKIO I Reset pin input LKRS I A/D pin input leakage current LKAD I OSCIN pin input leakage current LKOS ST92185B - ELECTRICAL CHARACTERISTICS Test Conditions External clock External clock TTL TTL CMOS CMOS Push-pull Ild=-0.8mA Push-pull ld=+1.6mA bidir. state ...
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... ST92185B - ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS PIN CAPACITANCE ( = 5V +/-10 70°C; unless otherwise specified Symbol Parameter C Pin Capacitance Digital Input/Output IO CURRENT CONSUMPTION ( = 5V +/-10 70°C; unless otherwise specified Symbol Parameter I Run Mode Current DD1 Run Mode Analog Current ...
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... Symbol Parameter T Jitter on RGB output jskw (*) The OSD jitter is measured from leading edge to leading edge of a single character row on consecutive TV lines. The value is an envelope of 100 fields ST92185B - ELECTRICAL CHARACTERISTICS Condition (1) OSCIN/2 as internal Clock Conditions 36 MHz Skew corrector clock frequency Value ...
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... ST92185B - ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS (Cont’d) OSD DAC CHARACTERISTICS (ROM DEVICES ONLY +/-10 70°C, unless otherwise specified Symbol Parameter Output impedance: FB,R,G,B Output voltage: FB,R,G,B code= 111 code= 011 code= 000 FB= 1 FB= 0 Global voltage accuracy OSD DAC CHARACTERISTICS (EPROM AND OTP DEVICES ONLY) ...
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... Sample time (3) it must be considered as the on-chip series resistance before the sampling capacitor (4) DNL ERROR= max {[V(i) -V(i-1)] / LSB-1} ABSOLUTE ACCURACY= overall max conversion error ST92185B - ELECTRICAL CHARACTERISTICS OSCIN divide by OSCIN divide 2;min/max by 1; min/max Core Clock issued by Timing Controller Value typ (*) ...
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... ST92185B - GENERAL INFORMATION 9 GENERAL INFORMATION 9.1 PACKAGE MECHANICAL DATA Figure 105. 56-Pin Shrink Plastic Dual In Line Package, 600-mil Width Figure 106. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width 172/178 Dim 50. 12. PDIP56S N Dim ...
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... PACKAGE MECHANICAL DATA (Cont’d) Figure 107. 64-Pin Thin Quad Flat Package Figure 108. 56-Pin Shrink Ceramic Dual In Line Package, 600-mil Width ST92185B - GENERAL INFORMATION CDIP56SW mm inches Dim Min Typ Max Min Typ Max A 1.60 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 B 0 ...
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... ST92185B - GENERAL INFORMATION Figure 109. 42-Pin Shrink Ceramic Dual In-Line Package, 600-mil Width Figure 110. 64-Pin Ceramic Quad Flat Package 174/178 Dim 36.68 37.34 38.00 1.444 1.470 1.496 D1 E1 14.48 14.99 15.49 0.570 0.590 0.610 e G 14.12 14.38 14.63 0.556 0.566 0.576 G1 18.69 18.95 19.20 0.736 0.746 0.756 G2 G3 11.05 11.30 11.56 0.435 0.445 0.455 G4 15 ...
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... Figure 111. ROM Factory Coded Device Types TEMP. DEVICE PACKAGE RANGE ST92185B - GENERAL INFORMATION 9.2.1 Transfer Of Customer Code Customer code is made up of the ROM contents and the list of the selected options (if any). The ROM contents are to be sent on diskette electronic means, with the hexadecimal file gener- ated by the development tool ...
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... ST92185B - GENERAL INFORMATION Customer Address Contact Phone No Reference/ROM Code *The ROM code name assigned by ST. STMicroelectronics reference: Device ST92185B1B1 [ ] ST92185B2B1 [ ] ST92185B3B1 Package : [ ] SDIP42 [ ] SDIP56 [ ] TQFP64 Temperature Range : Software Development: Special Marking: For marking, one line is possible with maximum 14 characters. Authorized characters are let- ters, digits, ’ ...
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... Non-linearity values in A/D Converter Analog Parameters Table. Modified Modified Section 4.2 on page 1.3 Modification of the absolute maximum rating of the Supply Voltage value in Main Changes 177. Updated Figure 3 on page 10 and 57. ST92185B - REVISION HISTORY 01/11/00 03/15/00 Figure 5 on page 12. Changed 11 Oct Table 9 on page 59. 16 Jan Section 8 on page 166 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...