ST92195B STMicroelectronics, ST92195B Datasheet

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ST92195B

Manufacturer Part Number
ST92195B
Description
32-64k Rom Hcmos Mcu With On-screen-display And Teletext Data Slicer
Manufacturer
STMicroelectronics
Datasheet

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January 2000
Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
0 C to +70 C operating temperature range
Up to 24 MHz. operation @ 5V 10%
Min. instruction cycle time: 165ns at 24 MHz.
32, 48, 56 or 64 Kbytes ROM
256 bytes RAM of Register file (accumulators or
index registers)
256 bytes of on-chip static RAM
2, 6 or 8 Kbytes of TDSRAM (Teletext and
Display Storage RAM)
28 fully programmable I/O pins
Serial Peripheral Interface
Flexible Clock controller for OSD, Data Slicer
and Core clocks running from a single low
frequency external crystal.
Enhanced display controller with 26 rows of
40/80 characters
– Serial and Parallel attributes
– 10x10 dot matrix, 512 ROM characters, defin-
– 4/3 and 16/9 supported in 50/60Hz and 100/
– Rounding, fringe, double width, double height,
Teletext unit, including Data Slicer, Acquisition
Unit and up to 8 Kbytes RAM for data storage
VPS and Wide Screen Signalling slicer (on
some devices)
Integrated Sync Extractor and Sync Controller
14-bit Voltage Synthesis for tuning reference
voltage
Up to 6 external interrupts plus one Non-
Maskable Interrupt
8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability
16-bit watchdog timer with 8-bit prescaler
One 16-bit standard timer with 8-bit prescaler
4-channel A/D converter; 5-bit guaranteed
able by user
120 Hz mode
scrolling, cursor, full background color, half-
intensity color, translucency and half-tone
modes
ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
32-64K ROM HCMOS MCU WITH
Device Summary
ST92T195B7
ST92E195B7
ST92195B1
ST92195B2
ST92195B3
ST92195B4
ST92195B5
ST92195B6
ST92195B7
Rich instruction set and 14 addressing modes
Versatile
Assembler,
Source
emulators with Real-Time Operating System
available from third parties
Pin-compatible EPROM and OTP devices
available
Device
See end of document for ordering information
Level
64K EPROM
development
32K ROM
32K ROM
32K ROM
48K ROM
48K ROM
56K ROM
64K ROM
Program
64K OTP
Memory
Linker,
PSDIP56
TQFP64
Debugger
C-compiler,
RAM
ST92195B
TDS
2K
6K
6K
6K
8K
8K
8K
8K
8K
tools,
and
VPS/
WSS
DATA BRIEFING
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
PSDIP56/
hardware
CSDIP56
/CQFP64
Package
including
Archiver,
TQFP64
Rev. 2.5
1/22
1

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ST92195B Summary of contents

Page 1

... Device Summary Program TDS Device Memory RAM ST92195B1 32K ROM 2K ST92195B2 32K ROM 6K ST92195B3 32K ROM 6K ST92195B4 48K ROM 6K ST92195B5 48K ROM 8K ST92195B6 56K ROM 8K ST92195B7 64K ROM 8K ST92T195B7 64K OTP 8K ST92E195B7 64K EPROM 8K DATA BRIEFING including Archiver, and hardware ...

Page 2

... ST9 core from I/O and data management processing tasks allowing criti- cal application tasks to get the maximum use of core resources. The ST92195B MCU supports low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 ST9+ Core ...

Page 3

... The SPI uses a single data line for data input and output. A second line is used for a syn- chronous clock signal. 1.1.11 Standard Timer (STIM) The ST92195B has one Standard Timer (STIM0) that includes a programmable 16-bit down counter and an associated 8-bit prescaler with Single and Continuous counting modes. ...

Page 4

... ST92195B - GENERAL DESCRIPTION INTRODUCTION (Cont’d) Figure 1. ST92195B Block Diagram Kbytes ROM 256 bytes RAM Kbytes TRI TDSRAM 256 bytes Register File 8/16-bit CPU MMU NMI INT[7:4] Interrupt INT2 Management INT0 ST9+ CORE OSCIN OSCOUT RCCU RESET RESETO 16-BIT ...

Page 5

... PIN DESCRIPTION Figure 2. 64-Pin Package Pin-Out 64 GND 1 AIN4/P0.2 P0.1 P0.0 CSO/RESET0/P3.7 P3.6 P3.5 P3 SDO/SDI/P5.1 INT2/SCK/P5 JTDO 16 16 N.C. = Not connected ST92195B - GENERAL DESCRIPTION P4.7/PWM7/EXTRG/STOUT P4.6/PWM6 P4.5/PWM5 P4.4/PWM4 P4.3/PWM3/TSLU/HT P4.2/PWM2 P4.1/PWM1 P4.0/PWM0 VSYNC HSYNC/CSYNC AVDD1 PXFM JTRST0 GND N.C. 32 5/22 ...

Page 6

... ST92195B - GENERAL DESCRIPTION PIN DESCRIPTION (Cont’d) RESET Reset (input, active low). The ST9+ is ini- tialised by the Reset signal. With the deactivation of RESET, program execution begins from the Program memory location pointed to by the vector contained in program memory locations 00h and 01h ...

Page 7

... PIN DESCRIPTION (Cont’d) Figure 4. ST92195B Required External components (56-pin package) +5V U1 P20 1 P2.0/INT7 RESETN P07 3 10k C2 R1 P0.7 P06 4 P0.6 P05 5 P0.5 P04 6 P0.4 S1 P03 7 D1 P0.3 P02 8 P0.2/AIN4 P01 9 1N4148 RST P0.1 P00 10 P0.0 L2 P37 11 P3.7/RESET0/CSO P36 12 P3.6 10uH P35 13 P3.5 P34 14 P3 ...

Page 8

... ST92195B - GENERAL DESCRIPTION PIN DESCRIPTION (Cont’d) Figure 5. ST92195B Required External Components (64-pin package 10k +5V 1N4148 RST C3 100nF L1 10uH C5 U1 10uF 1 VSS P02 2 P0.2/AIN4 P01 3 P0.1 P00 4 P0.0 P37 5 P3.7/RESET0/CSO P36 6 P3.6 P35 7 P3.5 P34 ...

Page 9

... P4 ST92195B - GENERAL DESCRIPTION Important : Note that open-drain outputs are for logic levels only and are not true open drain. 1.2.1 I/O Port Alternate Functions. Each pin of the I/O ports of the ST92195B may as- sume software programmable Alternate Functions (see Table 1). Alternate Functions I/O 9 I/O 8 AIN4 ...

Page 10

... ST92195B - GENERAL DESCRIPTION Pin No. Port General Purpose I/O Name TQFP64 SDIP56 P4 P4 All ports useable for general pur- P4 pose I/O (input, output or bidi- rectional 1.2.2 I/O Port Styles Pins Weak Pull-Up Port Style P0[7:0] no Standard I/O P2[5,4,3,2] no Standard I/O P2[1,0] no Schmitt trigger P3.7 yes Standard I/O P3[6,5,4] no Standard I/O P4[7:0] no Standard I/O ...

Page 11

... Example 2: PWM 0 output AF: PWM0, Port: P4.0 Write the port configuration bits (for output push- pull): P4C2.0=0 P4C1.0=1 P4C0.0=1 ST92195B - GENERAL DESCRIPTION Example 3: ADC analog input AF: AIN1, Port : P2.1, Port style: does not apply to analog inputs Write the port configuration bits: P2C2.1=1 P2C1.1=1 P2C0.1=1 ...

Page 12

... Start Device Size Address ST92195B1/B2/B3 32K 0000h ST92195B4/B5 48K 0000h ST92195B6 56K 0000h ST92195B7 64K 0000h Figure 6. ST92195B Memory Map 229FFFh max. 8 Kbytes TDSRAM 228000h SEGMENT 22h 64 Kbytes SEGMENT 21h 64 Kbytes 20FFFFh Internal RAM 256 bytes 20FF 00h SEGMENT 20h SEGMENT 0 ...

Page 13

... Exposure to maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Supply Voltage DD V Analog Supply Voltage (PLL) DDA f External Oscillator Frequency OSCE f Internal Clock Frequency (INTCLK) OSCI ST92195B - ELECTRICAL CHARACTERISTICS Value +0.3 ...

Page 14

... ST92195B - ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS ( = 5V +/-10 unless otherwise specified Symbol Parameter V Clock In high level IHCK V Clock in low level ILCK V Input high level IH V Input low level IL V Input high level IH V Input low level IL V Reset in high level ...

Page 15

... DD A Symbol Parameter T low level pulse width TpC+12 wLR T high level pulse width TpC+12 wHR TpC is the INTCLK clock period. ST92195B - ELECTRICAL CHARACTERISTICS Conditions min Condition s min notes 1,2; all On Timing Controller On notes 1,4 notes 1 HSYNC is driven by a 15625Hz clock HSYNC is driven by a 15625Hz clock. ...

Page 16

... ST92195B - ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS (Cont’d) SPI TIMING TABLE ( = 5V +/-10 Cload= 50pF Symbol Parameter T Input Data Set-up Time sDI T Input Data Hold Time hDI T SCK to Output Data Valid dOV T Output Data Hold Time hDO T SCK Low Pulse Width ...

Page 17

... C, unless otherwise specified Symbol Parameter Output impedance: FB,R,G,B Output voltage: FB,R,G,B code= 111 code= 011 code= 000 FB= 1 FB= 0 Global voltage accuracy ST92195B - ELECTRICAL CHARACTERISTICS Value Conditio ns min typical 300 500 Cload= 20pF RL = 100K 1.000 0.450 0.025 2.4 2.7 0 0.025 ...

Page 18

... ST92195B - ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS (Cont’d) A/D CONVERTER, EXTERNAL TRIGGER TIMING TABLE ( = 5V +/-10 unless otherwise specified Symbol Parameter T Pulse Width low T Pulse Distance high T Period/fast Mode ext T Start Conversion Delay str Core Clock issued by Timing Controller T Pulse Width ...

Page 19

... GENERAL INFORMATION 3.1 PACKAGE MECHANICAL DATA Figure 7. 56-Pin Shrink Plastic Dual In Line Package, 600-mil Width Figure 8. 64-Pin Thin Quad Flat Package L1 ST92195B - GENERAL INFORMATION Dim. Min A A1 0. 0.20 D 50. 12. 2.92 PDIP56S N Dim Min A A1 0.05 A2 1.35 1.40 1.45 0.053 0.055 0.057 B 0.30 0.37 0.45 0.012 0.015 0.018 C 0 ...

Page 20

... ST92195B - GENERAL INFORMATION PACKAGE MECHANICAL DATA (Cont’d) Figure 9. 56-Pin Shrink Ceramic Dual In Line Package, 600-mil Width Figure 10. 64-Pin Ceramic Quad Flat Package 20/22 mm Dim. Min Typ A A1 0.76 B 0.38 0.46 0.56 0.015 0.018 0.022 B1 0.76 0.89 1.02 0.030 0.035 0.040 C 0.23 0.25 0.38 0.009 0.010 0.015 D 50.04 50.80 51.56 1.970 2.000 2.030 D1 48.01 E1 14.48 14.99 15.49 0.570 0.590 0.610 e 1 ...

Page 21

... RANGE Figure 13. EPROM User Programmable Device Types TEMP. DEVICE PACKAGE RANGE ST92195B - GENERAL INFORMATION 3.2.1 Transfer Of Customer Code Customer code is made up of the ROM contents and the list of the selected options (if any). The ROM contents are to be sent on diskette electronic means, with the hexadecimal file gener- ated by the development tool ...

Page 22

... ST92195B - GENERAL INFORMATION Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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