ADN2806 Analog Devices, Inc., ADN2806 Datasheet - Page 19

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ADN2806

Manufacturer Part Number
ADN2806
Description
622 Mbps Clock And Data Recovery Ic
Manufacturer
Analog Devices, Inc.
Datasheet
V
V
VTH = ADN2806 THRESHOLD
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2806.
V1b
V2b
DIFF
DIFF
V1
V2
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
THE QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
= V2–V2b
1
LIM
V1b
V1
C
C
IN
IN
2
V2b
V2
PIN
NIN
Figure 21. Example of Baseline Wander
50Ω
50Ω
ADN2806
V
REF
Rev. 0 | Page 19 of 20
+
BUFFER
3
CDR
C
C
OUT
OUT
DATAOUTP
DATAOUTN
4
VREF
VTH
ADN2806

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