ADN2806 Analog Devices, Inc., ADN2806 Datasheet - Page 9

• Manufacturer Part Number: ADN2806
• Description: 622 Mbps Clock And Data Recovery Ic
• Manufacturer: Analog Devices, Inc.

Table 6. Internal Register Map
Reg
Name
FREQ0
FREQ1
FREQ2
MISC
CTRLA
CTRLB
CTRLC
1
Table 7. Miscellaneous Register, MISC
D7
x
Table 8. Control Register, CTRLA
F
D7
0
0
1
1
1
Table 9. Control Register, CTRLB
Config LOL
D7
0 = LOL pin normal operation
1 = LOL pin is static LOL
Table 10. Control Register, CTRLC
D7
Set to 0
All writeable registers default to 0x00.
Where DIV_F
REF
Range
D6
0
1
0
1
D6
x
R/W
R
R
R
R
W
W
W
D6
Set to 0
REF
19.44 MHz
38.88 MHz
77.76 MHz
155.52 MHz
is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section).
D5
x
Addr
0x4
0x0
0x1
0x2
0x8
0x9
0x11
Static LOL
D4
1 = Static LOL until reset
D5
Set to 0
0 = Waiting for next LOL
D7
MSB
MSB
0
x
Config
LOL
0
F
REF
Reset MISC[4]
D6
Write a 1 followed
by 0 to reset MISC[4]
1
D4
Set to 0
range
D6
MSB
x
Reset
MISC[4]
0
1
Data Rate/Div_F
D5
0
0
0
0
D3
Set to 0
D4
1
1
1
1
D5
x
System
reset
0
D3
0
0
0
0
System Reset
D5
Write a 1 followed by
0 to reset ADN2806
D2
Set to 0
REF
0 = Locked
LOL Status
D3
1 = Acquiring
Ratio
D2
1
1
1
1
Data rate/DIV_F
D4
Static
LOL
0
0
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32
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32
D3
LOL
status
Reset
MISC[2]
0
Measure Data Rate
Set to 1 to measure data rate
D1
REF
Data Rate Measurement Complete
D2
0 = Measuring data rate
1 = Measurement complete
ratio
D4
Set to 0
SQUELCH Mode
D1
0 = Squelch data outputs and
clock outputs
1 = Squelch data outputs or
clock outputs
D2
Data rate
measurement
complete
0
x
Reset MISC[2]
D3
Write a 1 followed
by 0 to reset MISC[2]
D1
x
Measure data rate
0
SQUELCH mode
Lock to Reference
D0
0 = Lock to input data
1 = Lock to reference clock
D2
Set to 0
Output Boost
D0
0 = Default output swing
1 = Boost output swing
D0
LSB
LSB
LSB
x
Lock to reference
0
Output boost
D1
Set to 0
ADN2806
D1
x
D0
Set to 0
D0
x