ADN2814 Analog Devices, Inc., ADN2814 Datasheet
ADN2814
Related parts for ADN2814
ADN2814 Summary of contents
Page 1
... The receiver front-end, loss-of-signal (LOS) detector circuit indicates when the input signal level has fallen below a user- adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2814 is available in a compact 5 mm × 5 mm, 32-lead LFCSP. FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN ...
Page 2
... ADN2814 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Jitter Specifications....................................................................... 4 Output and Timing Specifications ............................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Timing Characteristics..................................................................... 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. Interface Timing and Internal Register Description........... 10 Terminology ...
Page 3
... THRESH kΩ THRESH 2 DC-coupled 2 DC-coupled With respect to nominal With respect to nominal 10 Mb/s OC-12 OC-12 OC-3 OC-1 10 Mb/s See Table 13 In addition to REFCLK accuracy Data rate ≤ 20 Mb/s Data rate > 20 Mb/s Rev Page ADN2814 23 − 1, Min Typ Max Unit 1.8 2.8 V 2.0 V 2.3 2.5 2 3.3 mV p-p 500 μV 290 μ ...
Page 4
... PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW Jitter Peaking Jitter Generation Jitter Tolerance 1 Jitter tolerance of the ADN2814 at these jitter frequencies is better than what the test equipment is able to measure. Conditions Locked to 622.08 Mb/s , VEE = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2 F Conditions ...
Page 5
... 2 2 0.4 V − −2 Rev Page ADN2814 Typ Max Unit 1475 mV mV 320 400 mV 1200 1275 mV 100 Ω 115 220 ps 115 220 ps 800 840 ps 800 840 ps V 0.3 VCC V +10.0 μA ...
Page 6
... ADN2814 ABSOLUTE MAXIMUM RATINGS VCC = MIN MAX MIN MAX 0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Range ESD CAUTION ESD (electrostatic discharge) sensitive device ...
Page 7
... TIMING CHARACTERISTICS CLKOUTP DATAOUTP/ DATAOUTN Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP Figure 3. Differential Output Specifications 5mA R V LOAD DIFF 100Ω 100Ω 5mA SIMPLIFIED LVDS OUTPUT STAGE Figure 4. Differential Output Stage Rev Page ADN2814 ...
Page 8
... TEST2 Exposed Pad Pad 1 Type power analog input analog output digital input digital output. TEST1 1 PIN 1 INDICATOR VCC 2 VREF 3 ADN2814* NIN 4 PIN 5 TOP VIEW (Not to Scale) SLICEP 6 SLICEN 7 VEE 8 * THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND. ...
Page 9
... TYPICAL PERFORMANCE CHARACTERISTICS 100 1k R (Ω) TH Figure 6. LOS Comparator Trip Point Programming 10k 100k Rev Page ADN2814 ...
Page 10
... ADN2814 INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION 1 MSB = 1 S SLAVE ADDR, LSB = 0 (WR) A(S) S SLAVE ADDR, LSB = 0 (WR) A( START BIT A(S) = ACKNOWLEDGE BY SLAVE START BIT SLAVE ADDRESS SDA A6 A5 SCK S SLADDR[4... SDA t LOW SCK t HD;STA S SLAVE ADDRESS [6... SET BY PIN 19 Figure 7 ...
Page 11
... System Reset D5 D4 Write a 1 followed by Set reset ADN2814 Config LOS SQUELCH Mode Set Active high LOS 0 = SQUELCH CLK and DATA 1 = Active low LOS 1 = SQUELCH CLK or DATA Rev Page ADN2814 D1 D0 ...
Page 12
... Single-Ended vs. Differential AC coupling is typically used to drive the inputs to the quantizer. The inputs are internally dc biased to a common- mode potential of ~2.5 V. Driving the ADN2814 single-ended and observing the quantizer input with an oscilloscope probe at the point indicated in Figure 13 shows a binary signal with an average value equal to the common-mode potential and instantaneous values both above and below the average value ...
Page 13
... JITTER SPECIFICATIONS The ADN2814 CDR is designed to achieve the best bit- error-rate (BER) performance and to exceed the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia Technologies specification. Jitter is the dynamic displacement of digital signal edges from their long-term average positions, measured in unit intervals (UI), where bit period ...
Page 14
... ADN2814 THEORY OF OPERATION The ADN2814 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops, which share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter ...
Page 15
... The jitter accommodation is roughly 0 this region. The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 1.0 MHz at 622 Mb/s. Rev Page ADN2814 ...
Page 16
... ADN2814 FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION The ADN2814 acquires frequency from the data over a range of data frequencies from 10 Mb/s to 675 Mb/s. The lock detector circuit compares the frequency of the VCO and the frequency of the incoming data. When these frequencies differ by more than 1000 ppm, LOL is asserted. This initiates a frequency acquisition cycle ...
Page 17
... The I LOL bit. If there is ever an occurrence of a loss-of-lock condition, this bit is internally asserted to logic high. The MISC[4] bit remains high even after the ADN2814 has reacquired lock to a new data rate. This bit can be reset by writing a 1 followed Register Bit CTRLB[6] ...
Page 18
... Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. = 1/155.52 MHz. The ADN2814 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long supporting the 7-bit addresses plus the R/W bit. The ADN2814 has eight subaddresses to enable the user-accessible internal registers (see Table 6 through Table 10) ...
Page 19
... MHz. CTRLA[5:2] would be set to [0101], that is, 5, because 622.08 Mb/s/19.44 MHz = 2 In this mode, if the ADN2814 loses lock for any reason, it relocks onto the reference clock and continues to output a stable clock. While the ADN2814 is operating in lock-to-reference mode, if ...
Page 20
... The accuracy error of the reference clock is added to the accuracy of the ADN2814 data rate measurement. For example 100 ppm accuracy reference clock is used, the total accuracy of the measurement is within 200 ppm. ...
Page 21
... Use μF electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they should be placed between the IC power supply VCC and VEE, as close as possible to the ADN2814 VCC pins. VCC + 22μF 0.1μ ...
Page 22
... PDJ pspp < 0.01 UI p-p typical the rise time, which is equal to 0.22/BW, r where BW ~ 0.7 (bit rate). Note that this expression for t The output rise time for the ADN2814 is ~100 ps regardless of data rate. Rev Page −t/τ ); therefore, τ = 12t (−nT/RC) = 0.5t (1 − e )/0.6 ...
Page 23
... EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER DOES NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2814. THE QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT. ...
Page 24
... ADN2814 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 13. Look-Up Table Code F Code MID 0 5.3745e+ 5.3741e+ 5.4793e+ 5.5912e+ 5.7111e+ 5.8391e+ 5.9760e+ 6.1215e+ 6.2780e+ 6.4565e+ ...
Page 25
... Rev Page ADN2814 Code F MID 222 6.9873e+08 223 7.2525e+08 224 6.8793e+08 225 6.8789e+08 226 7.0135e+08 227 7.1567e+08 228 7.3102e+08 229 7.4741e+08 230 7 ...
Page 26
... PIN 1 INDICATOR VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 ADN2814ACPZ −40°C to 85°C ADN2814ACPZ-500RL7 1 −40°C to 85°C 1 ADN2814ACPZ-RL7 −40°C to 85°C EVAL-ADN2814EB Pb-free part. 5.00 0.60 MAX 0.50 BSC TOP 4.75 BSC SQ 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 COPLANARITY 0.20 REF 0.23 ...
Page 27
... NOTES Rev Page ADN2814 ...
Page 28
... ADN2814 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Patent Rights to use these components © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...