ADN2814 Analog Devices, Inc., ADN2814 Datasheet - Page 16

• Manufacturer Part Number: ADN2814
• Description: Continuous Rate 10 Mb/s To 675 Mb/s Clock And Data Recovery Ic With Integrated Limiting Amp
• Manufacturer: Analog Devices, Inc.

ADN2814
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
The ADN2814 acquires frequency from the data over a range of
data frequencies from 10 Mb/s to 675 Mb/s. The lock detector
circuit compares the frequency of the VCO and the frequency
of the incoming data. When these frequencies differ by more
than 1000 ppm, LOL is asserted. This initiates a frequency
acquisition cycle. The VCO frequency is reset to the bottom of
its range, which is 10 MHz. The frequency detector then
compares this VCO frequency and the incoming data frequency
and increments the VCO frequency, if necessary. Initially, the
VCO frequency is incremented in large steps to aid fast acquisi-
tion. As the VCO frequency approaches the data frequency, the
step size is reduced until the VCO frequency is within 250 ppm
of the data frequency, at which point LOL is deasserted.
Once LOL is deasserted, the frequency-locked loop is turned
off. The PLL/DLL pulls in the VCO frequency the rest of the
way until the VCO frequency equals the data frequency.
The frequency loop requires a single external capacitor between
CF1 and CF2, Pin 14 and Pin 15. A 0.47 μF ± 20%, X7R ceramic
chip capacitor with < 10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 μF capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 μF capacitor should be greater than 300 MΩ.
LIMITING AMPLIFIER
The limiting amplifier has differential inputs (PIN/NIN), which
are internally terminated with 50 Ω to an on-chip voltage
reference (VREF = 2.5 V typically). The inputs are typically
ac-coupled externally, although dc coupling is possible as long
as the input common-mode voltage remains above 2.5 V (see
Figure 27 to Figure 29 in the Applications Information section).
Input offset is factory trimmed to achieve better than 3.3 mV
typical sensitivity with minimal drift. The limiting amplifier can
be driven differentially or single-ended.
SLICE ADJUST
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise or
duty cycle distortion by applying a differential voltage input of
up to ±0.95 V to SLICEP/SLICEN inputs. If no adjustment of
the slice level is needed, SLICEP/SLICEN should be tied to
VEE. The gain of the slice adjustment is ~0.11 V/V.
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LOSS-OF-SIGNAL (LOS) DETECTOR
The receiver front-end LOS detector circuit detects when the
input signal level has fallen below a user-adjustable threshold.
The threshold is set with a single external resistor from Pin 9,
THRADJ, to VEE. The LOS comparator trip point vs. the
resistor value is illustrated in Figure 6. If the input level to the
ADN2814 drops below the programmed LOS threshold, the
output of the LOS detector, LOS Pin 22, is asserted to a Logic 1.
The LOS detector’s response time is ~500 ns by design, but is
dominated by the RC time constant in ac-coupled applications.
The LOS pin defaults to active high. However, by setting Bit
CTRLC[2] to 1, the LOS pin is configured as active low.
There is typically 6 dB of electrical hysteresis designed into the
LOS detector to prevent chatter on the LOS pin. If the input
level drops below the programmed LOS threshold causing the
LOS pin to assert, the LOS pin is not deasserted until the input
level has increased to 6 dB (2×) above the LOS threshold (see
Figure 19).
The LOS detector and the SLICE level adjust can be used
simultaneously on the ADN2814. This means that any offset
added to the input signal by the SLICE adjust pins does not
affect the LOS detector’s measurement of the absolute input
level.
Figure 19. LOS Detector Hysteresis
LOS OUTPUT
HYSTERESIS
LOS THRESHOLD
INPUT LEVEL
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