ADN2814 Analog Devices, Inc., ADN2814 Datasheet - Page 10

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ADN2814

Manufacturer Part Number
ADN2814
Description
Continuous Rate 10 Mb/s To 675 Mb/s Clock And Data Recovery Ic With Integrated Limiting Amp
Manufacturer
Analog Devices, Inc.
Datasheet
ADN2814
I
SDA
SCK
2
C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
START BIT
S = START BIT
A(S) = ACKNOWLEDGE BY SLAVE
S
S
SLAVE ADDR, LSB = 0 (WR)
SDA
SCK
A6
SLAVE ADDRESS
S
t
F
A5
S
SLAVE ADDR, LSB = 0 (WR) A(S)
SLADDR[4...0]
t
t
LOW
MSB = 1
HD;STA
1
A(S)
t
SET BY
PIN 19
SLAVE ADDRESS [6...0]
HD;DAT
SUB ADDR
t
R
A5
t
SU;DAT
WR
P = STOP BIT
A(M) = ACKNOWLEDGE BY MASTER
Figure 7. Slave Address Configuration
Figure 10. I
Figure 11. I
0
Figure 8. I
Figure 9. I
A(S)
ACK
Rev. 0 | Page 10 of 28
t
SUB ADDR
S
HIGH
t
SUB ADDRESS
F
0
2
2
2
2
C Data Transfer Timing
C Port Timing Diagram
C Write Data Transfer
SLAVE ADDR, LSB = 1 (RD)
C Read Data Transfer
A7
SUB ADDR[6...1]
t
SU;STA
0
A(S)
DATA
0
A0
S
A(S)
A(M) = LACK OF ACKNOWLEDGE BY MASTER
t
ACK
SU;STO
0
A(S) DATA A(M)
t
HD;STA
0 = WR
1 = RD
R/W
CTRL.
D7
DATA
X
DATA
DATA[6...1]
P
A(S)
t
BUF
t
R
P
S
DATA
D0
A(M)
ACK
P
STOP BIT
P

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