MB1511 Fujitsu, MB1511 Datasheet - Page 7

• Manufacturer Part Number: MB1511
• Description: Serial Input PLL Frequency Synthesizer
• Manufacturer: Fujitsu

(2)
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable
counter. Serial 19-bit data format is shown following page.
3. Serial Data Input Timing
Notes: Paranthesis data is used for setting divide ratio of programmable reference divider.
Note: Divide ratio: 0 to 127
7-bit Swallow Counter Divide Ratio
Divide Ratio
Programmable Divider
127
A
0
1
Data
Clock
LE
On rising edge of clock shifts one bit of data in the shift register.
C
t
1
~t
S
7
0
0
1
S18 = MSB
5
* (SW)
S
1
1 s
S
6
0
0
1
S
2
Divide ratio of swallow
t
S
5
0
0
1
counter setting bit
1
Control bit
LSB
S
3
S
4
0
0
1
S17
(S14)
S
4
S
3
0
0
1
S
5
S
2
0
0
1
S
6
S
1
0
1
1
S
7
t
2
Notes:
(S8)
11-bit Programmable Counter Divide Ratio
S
8
Divide Ratio
2047
S10
16
17
S
9
N
Divide ratio less than 16 is prohibited.
Divide ratio: 16 to 2047
S1 to S7: Swallow counter divide ratio setting bit. (0 to 127)
S8 to S18: Programmable counter divide ratio setting bit. (16 to 2047)
C: Control bit (sets as low level).
Data is input from MSB side.
10
S
Divide ratio of programmable
18
(S7)
S
0
0
1
S9
11
S
counter setting bit
17
S
0
0
1
12
S
16
S
0
0
1
13
S
15
S
0
0
1
t
14
S
3
S1 = LSB
14
S
0
0
1
(S1)
15
S
MSB
13
S
0
0
1
16
S
12
S
1
1
1
17
S
t
(C : CONTROL BIT)
11
4
S
0
0
1
C : CONTROL BIT
18
S
t
10
S
0
0
1
5
S
MB1511
9
0
0
1
S
8
1
1
1
7