MB15F04 Fujitsu Media Devices, MB15F04 Datasheet - Page 11
MB15F04
Manufacturer Part Number
MB15F04
Description
Dual Serial Input PLL Frequency Synthesizer
Manufacturer
Fujitsu Media Devices
Datasheet
1.MB15F04.pdf
(23 pages)
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Part Number:
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Note:
PHASE DETECTOR OUTPUT WAVEFORM
Do
Do
fr
fp
TX/RX
TX/RX
TX/RX
TX/RX
Phase error detection range = 2 to +2
Pulses on Do
LD output becomes low when phase error is t
LD output becomes high when phase error is t
t
t
t
WU
WU
WL
LD
(FC bit = High)
(FC bit = Low)
LD Output Logic Table
and t
< 16/fosc: i.e. t
Locking state / Power saving state
Locking state / Power saving state
Unlocking state
Unlocking state
> 8/fosc: i.e. t
WL
depend on OSCin input frequency as follows.
TX–PLL section
TX/RX
Z
Z
signals are output to prevent dead zone.
WU
WL
> 625ns when foscin = 12.8 MHz
< 1250ns when foscin = 12.8 MHz
t
WU
H
Locking state / Power saving state
Unlocking state
Locking state / Power saving state
Unlocking state
WL
WU
t
RX–PLL section
WL
or less and continues to be so for three cycles or more.
or more.
L
LD output
H
L
L
L
MB15F04
11