MB15F04 Fujitsu Media Devices, MB15F04 Datasheet - Page 8

• Manufacturer Part Number: MB15F04
• Description: Dual Serial Input PLL Frequency Synthesizer
• Manufacturer: Fujitsu Media Devices

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8
MB15F04
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Table.3 Test Purpose Bit Setting
LSB
Note: Divide ratio less than 5 is prohibited.
C
N
1
1
H
H
T
1
L
L
Divide
16383
ratio
Programmable Counter
(R)
C
N
2
5
6
2
CNT1, 2
N1 to N14
A1 to A7
SW
FC
LDS
NOTE: Data input with MSB first.
L
D
S
3
TX/RX
TX/RX
TX/
RX
W
S
4
H
H
T
2
L
L
14
R
0
0
1
TX/
RX
C
5
F
: Control bit
: Divide ratio setting bits for the TX section or RX section programmable counter
: Divide ratio setting bits for the TX section or RX section swallow counter
: Divide ratio setting bit for the prescaler (TX section : SW
: Phase control bit for the phase detector (TX section : FC
: LD/fout signal select bit
(5 to 2,047)
(0 to 127)
13
A
6
1
R
0
0
1
A
7
2
12
R
0
0
1
A
8
3
LD/fout pin state
Outputs fp
Outputs fp
Outputs fr
Outputs fr
11
R
0
0
1
Data Flow
A
9
4
10
A
5
10
R
0
0
1
TX
RX
TX
RX
11
A
6
R
9
0
0
1
12
A
7
13
N
1
R
8
0
0
1
14
N
2
R
7
0
0
1
15
N
3
R
16
6
0
0
1
N
4
TX
TX
, RX section: SW
, RX section : FC
17
N
5
R
5
0
0
1
18
N
6
R
4
0
0
1
19
N
7
RX
RX
20
N
8
)
) [Table. 7]
R
3
1
1
1
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 8]
21
N
9
R
2
0
1
1
10
22 23
N
MSB
11
N
R
1
1
0
1