MB84VA2003 Fujitsu Media Devices, MB84VA2003 Datasheet
MB84VA2003
Related parts for MB84VA2003
MB84VA2003 Summary of contents
Page 1
... One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture MB84VA2002: Top sector MB84VA2003: Bottom sector TM • Embedded Erase Algorithms Automatically pre-programs and erases the chip or any sector TM • ...
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... MB84VA2002 /MB84VA2003 -10 BLOCK DIAGRAM RESET CEf BYTE CE1s CE2s EXAMPLE OF CONNECTION WITH CHIPSET A[0:19] ROM_CS/ RAM_CS/ HWR/ LWR/ D[0:15] CHIPSET 2 - bit Flash Memory bit Static RAM ...
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... SA* CEf Table 1 Pin Configuration Function /MB84VA2003 - CE2s A 9 RY/ RESET BYTE Input/ Output I/O I ...
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... Notes: 1. Other operations except for indicated this column are inhibited can not apply CEf = V , CE1s = -10 Flash Memory +0.6 V MB84VA2002-10/MB84VA2003-10 –0.3 V 100 100 40 Table 2 User Bus Operations (BYTE=V CE1s CE2s ...
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... MB84VA2003 Sector Architecture - 16) FFFFFH 7FFFFH F0000H 78000H E0000H 70000H D0000H 68000H C0000H 60000H B0000H 58000H A0000H 50000H ...
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... MB84VA2002 /MB84VA2003 -10 Table 4 Sector Address Tables (MB84VA2002) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 ...
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... SA14 SA15 SA16 SA17 SA18 MB84VA2002 -10 Sector Address Tables (MB84VA2003 Address Range ( 00000H to 03FFFH 04000H to 05FFFH 06000H to 07FFFH 08000H to 0FFFFH 10000H to 1FFFFH X ...
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... Manufacturer’s Code MB84VA2002 Device Code MB84VA2003 * for Byte mode. -1 Table 6. 2 Expanded Autoselect Code Table Type Code Manufacturer’s Code 04H A MB84VA2002 (B) DAH (W) 22DAH Device Code MB84VA2003 (B) 5BH (W) 225BH (B): Byte mode (W): Word mode 8 - Byte V ...
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... SPA =Sector address to be protected. Set sector address (SA) and (A SD =Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector addresses. Note:This command is valid while Fast Mode. MB84VA2002 /MB84VA2003 -10 Flash Memory Command Definitions Fourth Bus Second Bus ...
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... No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 10 /MB84VA2003 - –0 ...
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... Min –500 Min — – 0.2 V, CE2s should be CE2s < 0.2V or CE2s > V CCS /MB84VA2003 -10 -10 Min. Typ. Max. Unit –1.0 — +1.0 –1.0 — +1.0 — — 22 — — — — 12 — ...
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... CE or BYTE Switching Low or High t ELFH Note: Test Conditions–Output Load: 1 TTL gate and 30 pF Input rise and fall times Input pulse levels: 0 3.0 V Timing measurement reference level Input: 1.5 V Output: 1 /MB84VA2003 -10 Description t CCR t CCR Description Test Setup -10 Unit — ...
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... Read Cycle (Flash) ADDRESSES CEf OE t OEH WE HIGH-Z DQ ADDRESSES t RH RESET HIGH-Z DQ MB84VA2002 /MB84VA2003 - Addresses Stable t ACC Output Valid t RC Addresses Stable t ACC Output Valid - HIGH ...
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... BYTE Switching Low to Output High-Z FLQZ — t BYTE Switching High to Output Active FLQV Note : 1. This does not include the preprogramming time. 2. This timing is for Sector Protection Operation. 14 /MB84VA2003 -10 Description Read Toggle and Data Polling (Note 2) ID -10 Unit Min. Typ. Max. ...
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... Figure indicates last two bus cycles out of four bus cycle sequence 6. These waveforms are for the x16 mode. The addresses differ from x8 mode. MB84VA2002 -10 Data Polling WHWH1 OUT 7 /MB84VA2003 - OUT 15 ...
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... D is the output of the data written to the device. OUT 5. Figure indicates last two bus cycles out of four bus cycle sequence 6. These waveforms are for the x16 mode. The addresses differ from x8 mode. 16 /MB84VA2003 -10 3rd Bus Cycle Data Polling 555H ...
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... WP t GHWL AAH DQ t VCS V CC Notes the sector address for Sector Erase. Addresses = 555H forChip Erase. 2. These waveforms are for the x16 mode. The addresses differ from x8 mode. MB84VA2002 /MB84VA2003 -10 2AAH 555H 555H WPH t DH ...
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... Valid Data (The device has completed the Embedded operation.) 7 • AC Waveforms for Taggle Bit during Embedded Algorithm Operations (Flash) CEf t OEH WE t OES OE DQ Data In 6 *DQ = Stops toggling. (The device has completed the Embedded operation /MB84VA2003 - OEH WHWH1 Invalid 0 6 ...
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... RESET, RY/BY Timing Diagram (Flash) WE RESET RY/BY • Timing Diagram for Word Mode Configuration (Flash) CE BYTE ELFH MB84VA2002 /MB84VA2003 -10 The rising edge of the last WE signal Entire programming or erase operations t BUSY READY Data Output Data Output ( ...
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... BYTE Timing Diagram for Write Operations (Flash BYTE • Temporary Sector Unprotection (Flash VIDR t VCS RESET CE WE RY/BY 20 /MB84VA2003 -10 Data Output Data Output ( ( FLQZ The falling edge of the last WE signal Input Valid t SET ...
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... Extended Sector Protection (Flash VCS RESET t VLHT t VIDR Add Data 60H SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 150 s (min) MB84VA2002 /MB84VA2003 -10 SPAX TIME-OUT 40H 60H -10 SPAX SPAY 60H 01H ...
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... Chip Enable (CE1s High or CE2s Low) to Output High Output Enable High to Output High-Z ODO t Output Data Hold Time OH • Read Cycle (Note 1) (SRAM) ADDRESSES CE1s CE2s OE DQ Note remains HIGH for the read cycle. 22 /MB84VA2003 - CO1 t COE t CO2 OEE ...
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... If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. MB84VA2002 /MB84VA2003 -10 Min. 100 60 80 ...
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... If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 24 /MB84VA2003 - ...
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... If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. MB84VA2002 /MB84VA2003 - ...
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... Chip Deselect to Data Retention Mode Time CDR t Recovery Time (Max –20°C to +40°C A • CE1s Controlled Data Retention Mode (Note 2.7 V See Note CE1s t CDR GND 26 /MB84VA2003 -10 (Flash) Limits Min. Typ. Max. — — 8 3,600 — 12 T.B.D 100,000 — — (SRAM ...
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... RESET, it can be protected the sector useing "Extended sector protect" command. MB84VA2002 /MB84VA2003 -10 DATA RETENTION MODE 0.2 V min. level (2.2 V), the standby current is given by I ...
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... PACKAGE PACKAGE DIMENSIONS 48-pin plastic BGA (BGA-48P-M06) 11.00±0.15(.433±.006) INDEX 1998 FUJITSU LIMITED MCM-M001-2 /MB84VA2003 -10 48-pin plastic FBGA (BGA-48P-M06) Note: The actual shape of coners may differ from the dimension. 1.40±0.20 (.055±.008) 0.30±0.10 (.012±.004) Ø0.40±0.10 (Ø ...
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... Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9805 FUJITSU LIMITED Printed in Japan MB84VA2002 /MB84VA2003 -10 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use ...