MB86291A Fujitsu Media Devices Limited, MB86291A Datasheet - Page 19

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MB86291A

Manufacturer Part Number
MB86291A
Description
Graphics Display Controller
Manufacturer
Fujitsu Media Devices Limited
Datasheet

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*1 : Applied only in PLL synchronization mode (CKS 0) . The reference clock is the internal PLL’s output with Cycle
*2 : Applied only in DCLKI synchronization mode (CKS
*3 : Based on the edge with VSYNC negated.
* : The EO output varies at the same time as VSYNC is asserted.
(2) Video Interface
CLK frequency
CLK H period
CLK L period
DCLKI frequency
DCLKI H period
DCLKI L period
DCLKO frequency
HSYNC input pulse width
HSYNC input setup time
HSYNC input hold time
VSYNC input pulse width
EO input setup time
EO input hold time
EO output delay time
HSYNC output delay time
VSYNC output delay time
CSYNC output delay time
GV output delay time
Clock
Input signals
Output signals
1/ (14 f
CLK
) .
Parameter
Parameter
Parameter
Symbol
Symbol
Symbol
t
t
t
t
t
t
t
t
WHSYNC0
WHSYNC1
WHSYNC1
t
t
f
DHSYNC
DCSYNC
SHSYNC
HHSYNC
DVSYNC
f
t
HDCLKI
t
LDCLKI
DCLKO
DCLKI
t
t
f
t
t
HCLK
LCLK
DEO
DGV
CLK
SEO
HEO
Condi-
Condi-
Condi-
tion
tion
tion
*1
*2
*2
*2
*3
*3
*
1) . The reference clock is DCLKI.
Min
Min
Min
1.5
1.5
1.5
1.5
1.5
25
25
10
10
10
10
5
5
3
3
1
Value
14.32
Value
Value
Typ
Typ
Typ
MB86291A
www.DataSheet4U.com
Max
Max
Max
67
67
11
11
11
11
11
HSYNC
1 cycle
MHz
clock
clock
MHz
MHz
unit
unit
unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19

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