L6223A ST Microelectronics, Inc., L6223A Datasheet - Page 8

• Manufacturer Part Number: L6223A
• Description: Dmos Programmable High Speed Unipolar Stepper Motor Driver
• Manufacturer: ST Microelectronics, Inc.

L6223A
Table 1
Figure 7: Internal Six-Bit Shift Register Bit Functions
CIRCUIT OPERATION (continued)
The FULL OPERATING MODE permits all the
driving possibilities. The 4 low side DMOS transis-
tors are drived directly by the 4 inputs IN1, IN2,
IN3, IN4 which define directly the phases configu-
ration. The chopping of the motor current can be
in open loop or in close loop. When in open loop
(fixed on-time block) the DA/OPLO pin is High
and the motor current is not controlled but it
mostly depends from the bits C2 nd C3. When in
close loop the DA/OPLO is Low and the output
current is controlled at a constant value defined
by the internal reference and by the sensing re-
sistor value. The internal reference depends by
the programming bits C0, C1, and by the input
configurations. During the power on sequence the
reset circuitry prevents current spikes disabling
the outputs and by resetting the memory.
Power Section
The basic concept for the current control is ex-
plained by examining the winding pair phase A
(MA) in Figure 24. With Q5 = ON, Q2 = OFF the
current rises until R
threshold value. The comparator output resets the
8/33
Device status
Programming
Simplified
Full mode
operating
operating
mode
mode
Bit C5
H
X
L
S
I
P
equals the comparator
Phase A
Phase A
Driver
IN1
L
Phase B
Phase A
Driver
driver
IN2
L
F/F and Q5 switches off. In this condition the cur-
rent decay path begins as shown in Figure 25.
The current value becomes I
double number of turns interested. In order to re-
duce the dissipation, Q2 is also driven on. Q5 re-
mains off (PWM off time) up to a new clock pulse
sets again the F/F. The winding current behaviour
is shown in Figure 26.
Since during PWM off time the current value is
half that of the on time and since in a typical ap-
plication Toff >>Ton, the device dissipation is fur-
ther reduced.
The five DMOS transistors are connected to the
”predriver stages” block, that drives the DMOS
gates, and interfaces them to the internal input
logic. The ”charge pump” provides correct voltage
for Q5 UPPER DMOS gate drive by using the ex-
ternal bootstrap capacitor.
Programming Mode
The Programming Mode is defined by the inputs
IN1=IN2=IN3=IN4=Low. When in PROGRAM-
MING MODE the outputs are disabled. The wave-
form shown in Fig. 8 represents one possible tim-
Phase B
Enable
driver
IN3
L
Alternative
Reduction
Phase B
Current
”LOW”
driver
IN4
L
DA/CLEV
Reductio
Current
”HIGH”
data in
Active
serial
p
/2, according to the
Open/Closed
Loop current
DA/OPLO
control
data in
serial