CMX969 Consumer Microcircuits Limited, CMX969 Datasheet - Page 13

• Manufacturer Part Number: CMX969
• Description: RD-LAP/MDC4800/Motient/ARDIS4-Level FSK Packet Data Modem
• Manufacturer: Consumer Microcircuits Limited

RD-LAP/MDC4800 Motient/ARDIS
CMX969
Note: The setting B7 = 1 and B6 = 1 cannot be used with 19200bps RD-LAP / 4800bps MDC4800 as this
would require a Xtal frequency above the oscillator operating range.
The CMX969 may also be used with a 9600bps RD-LAP system if the Xtal frequency is 4.9152 or 7.3728MHz
and Control register bits 7-6 set to ‘1 0’ or ‘1 1’
Control Register B5: Reserved for future use.
This bit should always be set to ‘0’.
Control Register B4: ALTCRC - Alternative CRC
This bit should always be set to ‘0’ for standard RD-LAP and MDC systems. Setting it to ‘1’ in RD-LAP mode
selects an alternative CRC generation/checking algorithm.
Control Register B3: ALTFILT - Alternative Filtering
This bit should always be set to ‘0’ for standard RD-LAP and MDC systems. Setting it to ‘1’ in RD-LAP mode
selects slightly different transmit and receive lowpass filter characteristics more suitable for some non-
standard systems.
Control Register B2: MDC - MDC Mode
If this bit is ‘0’ the CMX969 operates in RD-LAP mode, setting this bit to ‘1’ selects MDC mode. Changing
between RD-LAP and MDC modes will cancel any current task.
Control Register B1: FSTOL - Frame Sync Detect Tolerance
In RD-LAP mode this bit affects the number of errors tolerated by the Frame Sync detector when running SFS
or SFP tasks or AFSD. Approximately 3 bit errors are allowed when FSTOL = 0, 7 when FSTOL = 1.
In MDC mode this bit has no effect and the Frame Sync detector will accept up to 5 incorrect bits in a received
Frame Sync pattern when running the SFS task or AFSD.
Control Register B0: HOLD - Freeze Rx Level and Timing Corrections
Setting this bit to 1 disables the receive level and symbol timing error correction circuits.
1.5.5.3 Mode Register
The contents of this 8-bit write only register control the basic operating modes of the modem:
Mode Register B7: IRQNEN - IRQN Output Enable
When this bit is set to '1', the IRQN chip output pin is pulled low (to V ss ) whenever the IRQ bit of the Status
Register is a '1'.
2001 Consumer Microcircuits Limited
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D/969/5