CMX969 Consumer Microcircuits Limited, CMX969 Datasheet - Page 27

• Manufacturer Part Number: CMX969
• Description: RD-LAP/MDC4800/Motient/ARDIS4-Level FSK Packet Data Modem
• Manufacturer: Consumer Microcircuits Limited

RD-LAP/MDC4800 Motient/ARDIS
In transmit mode this bit is also set to '1' by a RESET task or by a change of the Mode Register TXRXN, ZP or
PSAVE bits, but in these cases the IRQ bit will not be set.
In transmit mode this bit is cleared to '0' within one symbol time after a task other than NULL or RESET is
written to the Command Register.
Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid level (half-way between
'+1' and '-1') signal will be sent to the low pass filter.
In receive mode this bit is set to ‘1’ - also setting the IRQ bit - when the Autonomous Frame Sync circuit is
enabled (by setting b7 of the Command Register) and a received Frame Sync pattern is detected. The bit is
cleared to ‘0’ immediately after reading the Status Register. To avoid confusion this bit is not set when Frame
Sync is detected as part of a RD-LAP SFP task.
In receive mode this bit is also cleared to '0' by a RESET task or by a change of the Mode Register TXRXN,
ZP or PSAVE bits.
Status Register B4: DIBOVF - De-Interleave Buffer Overflow
In receive mode this bit will be set to '1' - also setting the IRQ bit - when a RHB, RILB, RSID, R8B or R4S task
is written to the Command Register too late to allow continuous reception.
The bit is cleared to '0' immediately after reading the Status Register, by writing a RESET task to the
Command Register or by changing the TXRXN, ZP or PSAVE bits of the Mode Register.
In transmit mode this bit is '0'.
Status Register B3: CRCERR - CRC Checksum Error
In receive mode this bit will be updated at the end of a SFP, RHB, RILB or RSID task (when BFREE goes
high) to reflect the result of the receive CRC check. '0' indicates that the CRC was received correctly, '1'
indicates an error. In transmit mode this bit will be '0'.
Note that this bit should be ignored when an 'Intermediate' block (which does not have an integral CRC) is
received.
The bit is cleared to '0' by a RESET task, or by changing the TXRXN, ZP or PSAVE bits of the Mode Register.
Status Register B2: SRDY - 'S' Symbol Ready
In receive mode this bit is set to '1' whenever an 'S' symbol or channel status bit (other than the 94
been received. In RD-LAP mode the µC may then read the value of the symbol from the SVAL field of the
Status Register. In MDC mode the value of the received channel status bit will be in bit 0 of the Status
Register.
In transmit mode this bit is set to '1' whenever an 'S' symbol or channel status bit (other than the 94
been transmitted.
The bit is cleared to '0' immediately after a read of the Status Register, by a RESET task or by changing the
TXRXN, ZP or PSAVE bits of the Mode Register.
Status Register B1, B0: RD-LAP Mode: SVAL - Received 'S' Symbol Value
In receive RD-LAP mode these two bits reflect the value of the latest received 'S' symbol. In transmit mode,
these two bits will be '0'.
2001 Consumer Microcircuits Limited
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CMX969
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