GS1503 Gennum Corporation, GS1503 Datasheet - Page 50

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GS1503

Manufacturer Part Number
GS1503
Description
HD Embedded Audio Codec
Manufacturer
Gennum Corporation
Datasheet
2.6.3 Audio Clock Phase Locked Loop
Figure 39 shows the configuration for deriving the
6.144MHz audio clock in AES/EBU and serial audio output
modes. The GS1503 will internally synchronize the audio
output to the corresponding ACLK. This configuration is not
required when DEC_MODE is set HIGH. See the Reference
Design Section 3 for circuit specifics.
2.6.4 Audio Data Packet Detection
The audio data packet detect registers will be set HIGH
when a corresponding audio group DID has been detected
in the Chroma channel of the input video stream. Host
Interface register 013h, bits 7-4, report the individual audio
groups detected.
Register Settings
ADPG4_DET
ADPG3_DET
ADPG2_DET
ADPG1_DET
Y/C b / C r [19:0]
NAME
Audio group 4 data packet detection (1:Detection)
Audio group 3 data packet detection (1:Detection)
Audio group 2 data packet detection (1:Detection)
Audio group 1 data packet detection (1:Detection)
VIN[19:0]
ACLKA
ACLKB
GS1503
DESCRIPTION
Fig. 39 Block Diagram of GS1503 Audio Clock PLL
PLLCNTB
PLLCNTA
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
6.144MHz (128 fs)
6.144MHz (128 fs)
50
Audio Channels 1 & 2
Audio Channels 3 & 4
Audio Channels 5 & 6
Audio Channels 7 & 8
Pass
Filter
Pass
Filter
Low
Low
ADDRESS
013
24.576MHz
24.576MHz
VCXO
VCXO
BIT
7
6
5
4
SETTING
-
-
-
-
÷4
÷4
DEFAULT
15879 - 1
0
0
0
0

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