GS1532 Gennum Corporation, GS1532 Datasheet - Page 26

• Manufacturer Part Number: GS1532
• Description: Serializer For HD-SDI, Sd-sdi & DVB-ASI. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

3. DETAILED DESCRIPTION
3. DETAILED DESCRIPTION
3. DETAILED DESCRIPTION
3. DETAILED DESCRIPTION
3.1 GSPI - APPLICATION LAYER HOST INTERFACE
The GSPI, or Gennum Serial Peripheral Interface is a 4-wire
interface provided to allow the application layer to access
additional status information through configuration registers
in the GS1532.
The GSPI comprises a serial data input signal SDIN, serial
data output signal SDOUT, an active low chip select CS,
and a burst clock SCLK.
Because these pins are shared with the JTAG interface
port, an additional control signal pin JTAG/HOST is
provided.
3.1.1 Command Word Description
The command word consists of a 16-bit word transmitted
MSB first and contains a read/write bit, nine reserved bits
and a 6-bit address.
Command words are clocked into the deserializer on the
rising edge of the serial clock SCLK, which operates in a
burst fashion. The chip select CS signal must be active low
for at least 1.5ns (t
to ensure proper operation.
R/W: Read command if R/W='1', write command if R/W='0'.
RSV: Reserved for additional functionality
[A5:A0]: Address
GENNUM CORPORATION
MSB
MSB
D15
R/W
0
in Figure 10) before the first clock edge
D14
RSV
D13
RSV
D12
RSV
Application Host
D11
RSV
Fig. 7 GSPI Application Interface Connection
SDOUT
SCLCK
D10
SDIN
RSV
CS
Fig. 8 Command Word Format
Fig. 9 Data Word Format
D9
RSV
RSV
D8
26
D7
RSV
When JTAG/HOST is LOW, the GSPI interface is enabled.
When JTAG/HOST is HIGH, the JTAG interface is enabled.
When operating in GSPI mode, the SCLK, SDIN, and CS
signals are provided by the application interface. The
SDOUT pin is a high-impedance output allowing multiple
devices to be connected. The interface is illustrated in the
Figure 7.
All read or write access to the GS1532 is initiated and
terminated by the application host processor. Each access
always begins with a command / address word followed by
a data read or write to/from the GS1532.
Each command word must be followed by only one data
word to ensure proper operation.
3.1.2 Data Read or Write Access
Serial data is transmitted or received MSB first synchronous
with the rising edge of the serial clock SCLK. The chip
select CS signal must be active low for at least 1.5ns (t
Figure 10) before the first clock edge to ensure proper
operation. The first bit (MSB) of the serial output SDOUT is
available 12ns (t
SCLK edge of the read command word, the remaining bits
are clocked out on the negative edges of SCLK. Figures 10
and 11 illustrate the interface timing.
The device will not drive any signal out during the power up
phase or when the external RESET_TRST pin is asserted
LOW.
RSV
D6
SCLCK
SDIN
CS
SDOUT
D5
A5
GS1532
D4
A4
4
in Figure 11) following the last falling
D3
A3
D2
A2
D1
A1
D0
A0
LSB
LSB
21498 - 0
0
in