S3040A AMCC (Applied Micro Circuits Corp), S3040A Datasheet - Page 4
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S3040A
Manufacturer Part Number
S3040A
Description
Bicmos Pecl Clock Generator Sonet/sdh Clock Recovery Unit
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet
1.S3040A.pdf
(13 pages)
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CHARACTERISTICS
Performance
The S3040 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
Bellcore Specifications: GR-253-CORE, Issue 2, De-
cember 1995 and ITU-T Recommendations: G.958
document, when used with differential inputs and out-
puts.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. SONET input jitter
tolerance requirements are shown in Figure 3.
The measurement condition is the input jitter am-
plitude which causes an equivalent of 1 dB power
penalty.
Jitter Transfer
Jitter transfer function is defined as the ratio of jitter
on the output OC-N/STS-N signal to the jitter applied
on the input OC-N/STS-N signal versus frequency.
Jitter transfer requirements are shown in Figure 4.
The measurement condition is that input sinusoidal
jitter up to the mask level in Figure 3 be applied.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed 0.01 UI rms when a serial data input
with no jitter is presented to the serial data inputs.
(See Table 3).
4
S3040B
Figure 3. Input Jitter Tolerance Specification
Figure 4. Jitter Transfer Specification
1. Bellcore Specifications: GR-253- CORE, Issue 2, December 1995.
2. ITU-T Recommendations: G.958.
Input Jitter
Sinusodal
Amplitude
Transfer
SONET/SDH CLOCK RECOVERY UNIT
(UI p-p)
Jitter
OC/STS
OC/STS
Level
48
Level
P
48
1,2
1.5
0.4
15
Acceptable
(Hz)
10
f0
Frequency
f0
(MHz)
Frequency
(Hz)
600
f1
fc
2
fc
f1
April 6, 2000 / Revision NC
6000
(Hz)
f2
Range
slope = -20 dB/decade
f2
(kHz)
100
f3
(dB)
0.1
P
f3
(kHz)
1000
ft
ft