S3041 AMCC (Applied Micro Circuits Corp), S3041 Datasheet
S3041
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S3041 Summary of contents
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... The low jitter serial interface guarantees compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3042 is packaged in a 100 TQFP/TEP, offering designers a small package outline. OTX ORX S3040 OTX S3040 ORX ® S3042 S3042 S3042 S3042 S3041 ...
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... Frame detection 3. Serial-to-parallel conversion 4. 8-bit parallel output Internal clocking and control functions are transpar- ent to the user. Details of data timing can be seen in Figures 7 through 9. Suggested Interface Devices AMCC S3040 AMCC S3045 AMCC S3041 1:8 SERIAL TO PARALLEL FRAME BYTE DETECT ...
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SONET/SDH/ATM OC-48 1:8 RECEIVER SONET OVERVIEW Synchronous Optical Network (SONET standard for connecting one fiber system to another at the opti- cal level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single ...
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... OTHER OPERATING MODES Diagnostic Loopback When the Diagnostic Loopback Enable (DLEB) input is low, a loopback from the transmitter (S3041) to the receiver (S3042) at the serial data rate can be set up for diagnostic purposes. The differential serial output data and clock from the transmitter (S3041) (LSD/LSCLK) is routed to the receiver (S3042) (LSD/ LSCLK) in place of the normal data stream ...
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SONET/SDH/ATM OC-48 1:8 RECEIVER Table 2 . Input Pin Assignment and Descriptions ...
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S3042 Table 3. Output Pin Assignment and Descriptions ...
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SONET/SDH/ATM OC-48 1:8 RECEIVER Table 4. Common Pin Assignment and Description ...
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S3042 Figure 5. S3042 Pinout COREVCC 4 COREVCC 5 COREGND 6 COREGND 7 8 LVDSVCC LVDSVCC 9 10 LVDSGND 11 LVDSGND POCLKN 12 13 POCLKP 14 POUTN7 15 POUTP7 16 POUTN6 17 POUTP6 POUTN5 ...
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SONET/SDH/ATM OC-48 1:8 RECEIVER Figure 6. 100 TQFP/TEP Package TOP VIEW Thermal Management June 24, 1999 / Revision ...
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S3042 Table 5. Differential Low Swing CML Output DC Characteristics ...
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SONET/SDH/ATM OC-48 1:8 RECEIVER Table 8. Absolute Maximum Ratings ...
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S3042 Table 12. LVDS Input/Output Characteristics ...
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SONET/SDH/ATM OC-48 1:8 RECEIVER Table 13. AC Receiver Timing Characteristics ...
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S3042 RECEIVER FRAMING Figure 10 shows a typical reframe sequence in which a byte realignment is made. The frame and byte boundary detection is enabled by the rising edge of OOF. The byte alignment is made during the A1 data ...
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SONET/SDH/ATM OC-48 1:8 RECEIVER Figure 11. OOF Timing (FRAMEN = 1) OOF FP SEARCH Figure 12. FRAMEN Timing (OOF = 1) FRAMEN FP SEARCH Figure 13. Differential Voltage Measurement June 24, 1999 / Revision E BOUNDARY DETECTION ENABLED BOUNDARY DETECTION ...
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S3042 Figure 14. +5V Differential PECL Driver to S3042 Input AC Coupled Termination +5V 330 Figure 15. S3040 to S3042/S3044 Terminations S3040 SERDATOP/N SERCLKOP/N 16 SONET/SDH/ATM OC-48 1:8 RECEIVER Vcc -.65V .01 F 330 100 .01 F Vcc -.65V S3042/44 ...
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... SONET/SDH/ATM OC-48 1:8 RECEIVER Figure 16. S3041 to S3042 for Diagnostic Loopback LSCLKP/N Figure 17. S3042 LVDS Driver to S3045 LVDS Driver Figure 18. S3040/48/50 +5V PECL Output to CML Input AC Coupled Termination S3040/48/50 SERDATO SERCLKO June 24, 1999 / Revision E +3.3V S3041 LSDP/N +3.3V 100 275 275 S3042 POCLK POUT +5V .01 F .01 F +3.3V 100 ...
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S3042 Ordering Information – Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) ...