S3091 AMCC (Applied Micro Circuits Corp), S3091 Datasheet - Page 10

• Manufacturer Part Number: S3091
• Description: Sonet/sdh/atm OC-192 16:1 Transmitter
• Manufacturer: AMCC (Applied Micro Circuits Corp)

S3091 – SONET/SDH/ATM OC-192 16:1
Transmitter
Table 6. Input Pin Assignment and Descriptions (Continued)
Table 7. Output Pin Assignment and Descriptions
10
REFSEL
PHINITP
PHINITN
CLKSEL
SKEWSEL1
SKEWSEL0
TSDP
TSDN
PCLKP
PCLKN
155MCKP
155MCKN
77MCKP
77MCKN
LOCK-
ERRB
PHERRP
PHERRN
Pin Name
Pin Name
LVTTL
LVDS
LVDS
LVDS
LVDS
Level
LVTTL
LVTTL
LVTTL
CML
Diff.
LVDS
Level
I/O
I/O
I
I
I
I
O
O
O
O
O
O
Pin #
C13
D13
B13
J13
M2
A6
Pin #
C12
B11
A11
B10
A10
B12
A12
G1
B9
A9
J1
Reference Select. Used to select the reference clock frequency. See
Table 3.
Phase Initialization. Asynchronous input that initializes the phase
adjust circuit. (See Figure 9.)
Clock Select. Used to select between the 622.08 MHz or 311.04 MHz
dual edge clock on the PICLKP/N. See Table 4.
Allows magnitude error in delaying the 311 PICLK to compensate for
the variations in the data valid window due to Inter-Symbol Interference
(ISI) and static skew. See Table 5.
Transmit Serial Data. Serial data stream signals, normally con-
nected to an optical transmitter module. Use Coplanar Waveguide
Structure for best results. See Layout Recommendation application
note. See Characterization Report for S
Parallel Clock. A 622.08 MHz clock. It is normally used to coordi-
nate transfers between upstream logic and the S3091 device.
155.52 MHz Clock Output. 155.52 MHz clock output from the
clock synthesizer. The output should be connected to the reference
clock input of the external clock recovery function (such as the
S3092). Pull-down resistors may be removed to minimize power.
77.76 MHz Clock Output. 77.76 MHz clock output from the clock
synthesizer. For test purposes only. Pull-down resistors may be
removed to minimize power.
Lock Error/Phase Error. Active Low. Goes inactive after an inter-
nal delay and the PLL has locked to the clock provided on the REF-
CLK pins. LOCKERRB goes active for at least 100 ns when
PHERR goes active. LOCKERRB stays active as long as PHERR
is active. LOCKERRB is an asynchronous output.
Phase Error. Pulses High during each PCLK cycle for which there
is a potential set-up/hold timing violation between the internal byte
clock and PICLK timing domains.
Description
Description
Revision A – February 22, 2002
DEVICE SPECIFICATION
22
plot.