IDT82P2288 Integrated Device Technology, Inc., IDT82P2288 Datasheet - Page 111

• Manufacturer Part Number: IDT82P2288
• Description: 8 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2288
5
5.1
5.1.1
5.1.1.1
Programming Information
T1/J1 Reg
00C ~ 00D
X2D ~ X30
001 ~ 003
011 ~ 01F
(Hex)
X2A
X2B
X2C
00A
00B
00E
00F
X20
X21
X22
X23
X24
X25
X26
X27
X28
X29
X31
X32
X33
000
004
005
006
007
008
009
010
In the ‘Reg’ column, the ‘X’ represents 0 ~ 7, corresponding to the eight links.
PROGRAMMING INFORMATION
REGISTER MAP
T1/J1 MODE
LINKSEL2 LINKSEL1 LINKSEL0
Direct Register
DONE
DAT7
Bit 7
INT8
ID7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BPV_INS
WDAT6
EQ_ON
DAT6
DLLP
Bit 6
INT7
ID6
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TJITT_TES
RJITT_TES
T_TERM2 T_TERM1 T_TERM0
DFM_ON
WDAT5
SLICE1
SCAL5
RO22
DAT5
SLLP
Bit 5
INT6
ID5
UI1
T
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RJA_LIMT
TJA_LIMT
EXZ_DEF EXZ_ERR1 EXZ_ERR0 CNT_MD
RSLVCK
WDAT4
SLICE0
R_OFF
T_OFF
SCAL4
RO21
SRLP
DAT4
T_HZ
LOS4
Bit 4
INT5
ID4
UI0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LEVEL1
UPDW1
WDAT3
ADDR3
SAMP3
PULS3
SCAL3
RJA_E
RMUX
TJA_E
MON3
RO20
DAT3
T1/J1
LOS3
Bit 3
INT4
ID3
-
-
-
-
-
-
-
-
-
-
-
-
-
100
R_TERM2 R_TERM1 R_TERM0 Transmit And Receive Termi-
TJA_DP1
RJA_DP1
LEVEL0
UPDW0
MTSDA
ADDR2
SAMP2
WDAT2
PULS2
SCAL2
MON2
DF_IE
RO12
LOS2
DAT2
Bit 2
INT3
FM1
RLP
LAC
ID2
-
-
-
-
-
-
-
-
-
-
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RJA_DP0
TJA_DP0
TSLVCK
WDAT1
ADDR1
SAMP1
PULS1
SCAL1
RAISE
MON1
RO11
DAT1
LOS1
DIR1
Bit 1
INT2
MG1
FM0
ALP
ID1
-
-
-
-
-
-
-
-
-
-
-
CNT_TRF Maintenance Function Control
TEMODE T1/J1 Or E1 Mode
RJA_BW Receive Jitter Attenuation Con-
TJA_BW Transmit
TMOVE
WDAT0
LOS_IE
ADDR0
SAMP0
TMOVI
PULS0
SCAL0
MON0
TMUX
R_MD
RO10
T_MD
DAT0
LOS0
ATAO
Bit 0
DIR0
INT1
MG0
DLP
ID0
-
-
-
-
-
-
Backplane Global Configura-
Chip ID For Octal Transceiver
Reserved
Software Reset
G.772 Monitor Control
GPIO Control
Reference Clock Output Select
Reserved
Interrupt Requisition Link ID
Timer Interrupt Control
Timer Interrupt Indication
Reserved
PMON Access Port
PMON Access Data
tion
Reserved
Configuration
Transmit Configuration 0
Transmit Configuration 1
Transmit Configuration 2
Transmit Configuration 3
Transmit Configuration 4
figuration
Receive Configuration 0
Receive Configuration 1
Receive Configuration 2
Maintenance Function Control
0
Maintenance Function Control
1
Reserved
2
nation Configuration
Interrupt Enable Control 0
Register Name
Jitter
Attenuation
March 22, 2004
Reference
P 120
P 121
P 122
P 123
P 124
P 125
P 126
P 126
P 127
P 128
P 129
P 130
P 131
P 132
P 133
P 133
P 114
P 114
P 115
P 116
P 117
P 118
P 118
P 118
P 119
P 119
P 113
Page
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